Abstract: Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.

Abstract: Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.

Abstract: Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.

Abstract: Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.

Abstract: Embodiments of the present invention relate to meeting latency constraints in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synthesis under latency constraints is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. Each of the plurality of neurosynaptic cores is modeled as a node in a placement graph. The graph has a plurality of edges. A weight is assigned to each of the plurality of edges based on a spike frequency. An arrangement of the neurosynaptic cores is determined. The arrangement comprises a length of each of the plurality of edges. A maximum length is compared to the length of each of the plurality of edges. The weight of at least one of the plurality of edges is increased where the length is greater than the maximum length.

Abstract: A slew-based effective capacitance (Ceff) is used to compute gate output slew during early synthesis of an integrated circuit design. A ? model is constructed for the gate and reduced to two parameters which are used to compute a slew value for the model, given a slew definition. A capacitance coefficient is then calculated as a function of this slew value. The effective capacitance is the product of the coefficient and the total capacitance of the ? model. The output slew of the gate may in turn be computed using the slew-based Ceff. The coefficient may be computed by iteratively solving an equation representing output voltage over time dependent on the first and second parameters, by directly solving a closed-form equation which is a function of the first and second parameters, or by looking up the capacitance coefficient in a table indexed by the first and second parameters.

Abstract: A mechanism is provided for addressing coupled noise-based violations. For each net in an integrated circuit (IC) design, a determination is made as to whether an associated delta wire delay is below a predetermined threshold. Responsive to the associated delta wire delay failing to be below the predetermined threshold, a subset of nets is formed. For each net in the subset of nets, a stage delay side model of the net is adjusted to emulate a noise impact on timing of the net and an optimization is applied using the stage delay side model of the net. A full retiming of the set of nets is then performed. For each net in the subset of nets a determination is made as to whether the net has degraded slack and, responsive to the net having degraded slack, the applied optimization is backed out.

Abstract: A mechanism is provided for addressing coupled noise-based violations. For each net in an integrated circuit (IC) design, a determination is made as to whether an associated delta wire delay is below a predetermined threshold. Responsive to the associated delta wire delay failing to be below the predetermined threshold, a subset of nets is formed. For each net in the subset of nets, a stage delay side model of the net is adjusted to emulate a noise impact on timing of the net and an optimization is applied using the stage delay side model of the net. A full retiming of the set of nets is then performed. For each net in the subset of nets a determination is made as to whether the net has degraded slack and, responsive to the net having degraded slack, the applied optimization is backed out.

Abstract: An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.

Abstract: Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.

Abstract: Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.

Abstract: Embodiments of the present invention relate to meeting latency constraints in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synthesis under latency constraints is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. Each of the plurality of neurosynaptic cores is modeled as a node in a placement graph. The graph has a plurality of edges. A weight is assigned to each of the plurality of edges based on a spike frequency. An arrangement of the neurosynaptic cores is determined. The arrangement comprises a length of each of the plurality of edges. A maximum length is compared to the length of each of the plurality of edges. The weight of at least one of the plurality of edges is increased where the length is greater than the maximum length.

Abstract: Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI/PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI/PO.

Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.

Abstract: Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI/PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI/PO.

Abstract: A computer-based system and method for modeling integrated circuit congestion and wire distribution determines a boundary where a tile congestion corresponding to a first layer group is equivalent to a first blockage ratio corresponding to a second layer group, formulates a piece-wise linear formula that relates the tile congestion to a number of wires of a two-dimensional tile, and distributes a portion of the number of wires to a layer of the tile based on the tile congestion.

Abstract: A slew-based effective capacitance (Ceff) is used to compute gate output slew during early synthesis of an integrated circuit design. A ? model is constructed for the gate and reduced to two parameters which are used to compute a slew value for the model, given a slew definition. A capacitance coefficient is then calculated as a function of this slew value. The effective capacitance is the product of the coefficient and the total capacitance of the ? model. The output slew of the gate may in turn be computed using the slew-based Ceff. The coefficient may be computed by iteratively solving an equation representing output voltage over time dependent on the first and second parameters, by directly solving a closed-form equation which is a function of the first and second parameters, or by looking up the capacitance coefficient in a table indexed by the first and second parameters.

Abstract: A computer-based system and method for modeling integrated circuit congestion and wire distribution determines a boundary where a tile congestion corresponding to a first layer group is equivalent to a first blockage ratio corresponding to a second layer group, formulates a piece-wise linear formula that relates the tile congestion to a number of wires of a two-dimensional tile, and distributes a portion of the number of wires to a layer of the tile based on the tile congestion.

Abstract: A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design.

Abstract: A computer-based system and method for modeling integrated circuit congestion and wire distribution determines a boundary where a tile congestion corresponding to a first layer group is equivalent to a first blockage ratio corresponding to a second layer group, formulates a piece-wise linear formula that relates the tile congestion to a number of wires of a two-dimensional tile, and distributes a portion of the number of wires to a layer of the tile based on the tile congestion.