Abstract: Method and apparatus for generating cursors for display by a color raster graphic system. The cursors displayed can assume any one of a plurality of forms. Each cursor has predetermined boundaries and includes all pixel positions of the raster within its boundaries. One pixel position is designated as the origin of the cursor and selected ones of the pixel positions for each form of the cursor will display the cursor color and intensity. The address of the origin of a cursor and its form are designated by the graphic controller of the system. The address of the origin is compared with the addresses of the pixels produced by the raster scan logic, and, when the same, the form number and the x and y coordinates, the addresses of the pixel positions of the cursor relative to the origin thereof, are produced and applied to a read-only memory which produces cursor control signals stored at the addressed locations of the cursor memory.

Abstract: A display memory which stores information to be displayed on a raster scan CRT comprises a first storage element for storing dot information, a second storage element for storing behavior information, and a third storage element for storing characteristic information. The first, second, and third storage element are each arranged in an nxm plane where m is an addressable location and each addressable location within each plane has n bits of information. Further, each of the first, second, and third storage elements has address terminals each operatively connected to a display address bus adapted to receive address information from a CPU.Control logic receives address signals, data signals, and control signals from the CPU. The control logic generates enable control signals to selectively enable access to predetermined combinations of said first, second, and third storage elements in response to the address, data, and control signals from the CPU.

Abstract: Apparatus for controlling the colors displayed by a raster graphic system. Information stored at each addressable location of a RAM includes a set of behavior bits and a set of control bits. These bits are read out of memory during each memory read cycle. The control bits are stored in a shift register and the behavior bits are applied to an escape code detector and may be stored in a foreground or a background behavior register if enabled by the detector. One control bit is shifted out of the shift register each pixel clock pulse. This control bit determines the register from which the behavior bits are selected to form a color index. The index includes behavior bits from the selected register and the control bit for the pixel being scanned. This index is applied to a color look-up memory which produces color control signals which are applied to D/A converters, the outputs of which control the color and intensity of each pixel of the raster.

Abstract: Method and apparatus for controlling the display of a raster scan color cathode ray tube. The tube is provided with an orthogonal array of picture elements (pixels) with each picture element having a unique binary address. An addressable memory having memory locations with addresses corresponding to those of the picture element has stored in such memory locations an address of a location in a color look-up memory for an alphanumeric color, for a graphic color and priority signals. In the color look-up memory at the addressed locations is stored binary signals representing the color and intensity of a pixel. In synchronism with the raster scan of the picture elements of the cathode ray tube, there is read from the memory graphic color addresses, alphanumeric color addresses and priority signals for each pixel. One of the addresses, either the graphic or alphanumeric, is applied to the color look-up memory, with the address that is applied being determined by the binary priority signals.

Abstract: Method and apparatus for filling polygons displayed by a color CRT monitor of a raster graphic system. A graphic controller produces control signals which control the mode of operation of the system, two of which are a fast polygon write, or fast-fill write, mode and a fast polygon display, or display fast-fill, mode. When the system is in the fast polygon write mode, the graphic controller reads fast-fill toggle bits from a frame memory of boundary pixels defining initial and terminal pixels of each fill element. The fast-fill toggle bits of boundary pixels are set if the toggle bit read from memory was not set and, if set, it will reset it. In the fast polygon display mode, the system senses the initial boundary pixel of each fill element by its fast-fill toggle bit being set and applies the color address of the initial boundary pixel to a color look-up memory until the terminal pixel of the fill element is read from the memory.

Abstract: In a computer control system a central processor unit (CPU) is provided as a primary control center. A data bus interface controller is connected to interface between the CPU and a serial data communication bus. The interface control unit controls the traffic on the data bus as well as interfacing the format between serial data on the data bus and the parallel data receivable by the CPU. A plurality of process interface units are connected to the serial data bus. Each of these process interface units (PIU) has a plurality of process input/output devices connected thereto and controlled thereby. The PIU's exercise a significant amount of control capability including having an internal microprocessor unit. By performing many of the functions heretofore provided by the central processor unit, the PIU significantly reduces the amount of data which must be transmitted via the serial data bus to the CPU.