Patents by Inventor Charles J. DeVane
Charles J. DeVane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9774699Abstract: A mechanism for converting a graphical model of a system into an intermediate representation (IR) of a model is discussed. The mechanism alters the IR, and uses the altered IR to create a new or updated graphical model of the system that may be viewed and simulated by a user. Once the user is satisfied with the alterations to the IR, the IR or the graphical model may be used to generate code in a target language to enable the building of the physical system being designed. The use of the altered IR to generate a new or updated graphical model allows a more efficient and customizable design and simulation process than is typically found by simulating code that has been converted to target languages. The generation of the graphical model based on the altered IR allows a user to visually inspect the changes to the system, and the simulation of the graphical model based on the altered IR allows corrective action to be taken to account for any changes that occurred during the transformation of the model.Type: GrantFiled: September 20, 2005Date of Patent: September 26, 2017Assignee: The MathWorks, Inc.Inventors: Brian K. Ogilvie, Charles J. Devane, Kiran Kumar Kintali, Donald Paul Orofino, II
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Patent number: 8984496Abstract: The present invention provides systems and methods which allow the translation of a first representation into an intermediate representation and then into a target representation. The first representation can take numerous forms, including a system model that contains hardware components, software components or some combination thereof. Additionally, the target representation can be in the form of a desired system implementation. The intermediate representation generated from the first representation can include both parallel and serial processes from the first representation. This intermediate representation then uses both serial and parallel processing techniques operating on the system model from within a single intermediate representation to translate the system model of the first representation into a target representation. The target representation may be in a format that is readily used in the creation of a system implementation by a user.Type: GrantFiled: May 16, 2005Date of Patent: March 17, 2015Assignee: The MathWorks, Inc.Inventors: Charles J. Devane, Kiran Kumar Kintali
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Patent number: 8839193Abstract: A technical computing environment may include a modeling component to facilitate construction of a model and a code generation component. The modeling component may include an input component to receive one or more input signals through an interface protocol, and one or more components to receive one or more parameters, corresponding to the input signals received using the interface protocol, and to operate on the one or more parameters. The code generation component may include a code generator to generate, from the model, programming code compatible with a target environment, and an output interface to output the programming code.Type: GrantFiled: January 24, 2012Date of Patent: September 16, 2014Assignee: The Mathworks, Inc.Inventors: Charles J. Devane, Darel Allen Linebarger, Donald Paul Orofino
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Patent number: 8589870Abstract: A modeling system includes a graphical programming environment that receives a first graphical model from a user. The system may also receive a configuration control set for the first graphical model. A code generation engine converts the first graphical model into an intermediate representation (IR). A second graphical model is created from the IR and the configuration control set. The second graphical model is displayed to the user, and may be subject to one or more modifications. Code in a target language may be generated from the second graphical model.Type: GrantFiled: July 17, 2007Date of Patent: November 19, 2013Assignee: The Math Works, Inc.Inventors: Brian K. Ogilvie, Charles J. Devane, Kiran Kumar Kintali, Donald Paul Orofino, II
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Patent number: 8166456Abstract: A programming language type system includes, in a memory, a set of numeric type including integer types, fixed-point types and floating-point types, a set of type propagation rules to automatically determine result types of any combination of integer types, fixed-point types and floating-point types, constant annotations to explicitly specify a result type of a literal constant, context-sensitive constants whose type is determined from a context of a constant according to the set of type propagation rules, an assignment operator to explicitly specify a type of a value or computation, and operator annotations to explicitly specify a result type of a computation.Type: GrantFiled: November 26, 2008Date of Patent: April 24, 2012Assignee: The MathWorks, Inc.Inventor: Charles J. Devane
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Patent number: 7885792Abstract: A method includes combining functionality from a matrix language programming environment, a statechart programming environment and a block diagram programming environment into an integrated programming environment. The method can also include generating computer instructions from the integrated programming environment in a single user action. The integrated programming environment can support fixed-point arithmetic.Type: GrantFiled: April 15, 2003Date of Patent: February 8, 2011Assignee: The MathWorks, Inc.Inventor: Charles J. Devane
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Patent number: 7885800Abstract: Methods and systems for providing a synchronous model in a modeling environment are disclosed. The predetermined operations of the model, such as a transition to a state in a state-based modeling environment, are implicitly synchronized with a signal selected by users, such as a clock signal. The predetermined operations of the model may be synchronized on a rising and/or falling edge of the clock signal. The synchronization of the operations is guarded in which the predetermined operation of the model occurs only on the synchronization signal selected by the users while other operations may occur at any time when the model is activated.Type: GrantFiled: August 18, 2004Date of Patent: February 8, 2011Assignee: The MathWorks Inc.Inventors: Zhihong Zhao, Donald Paul Orofino, II, Brian K. Ogilvie, Charles J. Devane
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Patent number: 7523443Abstract: A programming language type system includes, in a memory, a set of numeric type including integer types, fixed-point types and floating-point types, a set of type propagation rules to automatically determine result types of any combination of integer types, fixed-point types and floating-point types, constant annotations to explicitly specify a result type of a literal constant, context-sensitive constants whose type is determined from a context of a constant according to the set of type propagation rules, an assignment operator to explicitly specify a type of a value or computation, and operator annotations to explicitly specify a result type of a computation.Type: GrantFiled: April 15, 2003Date of Patent: April 21, 2009Assignee: The MathWorks, Inc.Inventor: Charles J. DeVane
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Publication number: 20090077353Abstract: A programming language type system includes, in a memory, a set of numeric type including integer types, fixed-point types and floating-point types, a set of type propagation rules to automatically determine result types of any combination of integer types, fixed-point types and floating-point types, constant annotations to explicitly specify a result type of a literal constant, context-sensitive constants whose type is determined from a context of a constant according to the set of type propagation rules, an assignment operator to explicitly specify a type of a value or computation, and operator annotations to explicitly specify a result type of a computation.Type: ApplicationFiled: November 26, 2008Publication date: March 19, 2009Applicant: The MathWorks, Inc.Inventor: CHARLES J. DEVANE
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Publication number: 20040210869Abstract: A programming language type system includes, in a memory, a set of numeric type including integer types, fixed-point types and floating-point types, a set of type propagation rules to automatically determine result types of any combination of integer types, fixed-point types and floating-point types, constant annotations to explicitly specify a result type of a literal constant, context-sensitive constants whose type is determined from a context of a constant according to the set of type propagation rules, an assignment operator to explicitly specify a type of a value or computation, and operator annotations to explicitly specify a result type of a computation.Type: ApplicationFiled: April 15, 2003Publication date: October 21, 2004Inventor: Charles J. DeVane
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Publication number: 20040210615Abstract: A method includes combining functionality from a matrix language programming environment, a statechart programming environment and a block diagram programming environment into an integrated programming environment. The method can also include generating computer instructions from the integrated programming environment in a single user action. The integrated programming environment can support fixed-point arithmetic.Type: ApplicationFiled: April 15, 2003Publication date: October 21, 2004Inventor: Charles J. Devane
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Patent number: 5548719Abstract: A system and method for analyzing large logic traces, with the system having an input for regular expressions, a generator for receiving the regular expressions and generating finite automata which use arithmetic/logic expressions that permit the use of a substantially infinite alphabet, an input for a large trace array, and an analyzer for searching the large trace array with the finite automata, with the analyzer producing results of the search.Type: GrantFiled: April 14, 1995Date of Patent: August 20, 1996Assignee: Digital Equipment CorporationInventors: Charles J. DeVane, Arthur J. Beaverson
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Patent number: 5299206Abstract: A system and method for analyzing complex overlapping sequences of events in trace arrays, with the system having an input for receiving regular expressions that have been grouped in a predetermined manner, a generator for receiving the grouped regular expressions and generating multiple finite automata based on the groupings of regular expressions, with each finite automaton being generated using arithmetic/logic expressions to permit the use of a substantially infinite alphabet, an input for the trace array, and an analyzer for searching the trace array simultaneously with the multiple finite automata and providing a way by which the multiple finite automata may communicate with one another during searching, with the analyzer further outputting the results of the search.Type: GrantFiled: October 24, 1991Date of Patent: March 29, 1994Assignee: Digital Equipment CorporationInventors: Arthur J. Beaverson, Charles J. DeVane
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Patent number: 5228066Abstract: A circuit that may be implemented in a computer system that will measure the maximum and minimum time intervals for system elements to respond to a request for data or information. The circuit includes control logic that controls operation of the circuit, an up-counter and a down-counter that are used together for measuring the maximum or minimum response time interval, and a display for displaying the maximum or minimum response time interval that is measured during a test period.Type: GrantFiled: April 22, 1992Date of Patent: July 13, 1993Assignee: Digital Equipment CorporationInventor: Charles J. DeVane
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Patent number: 5187676Abstract: A high-speed pseudo-random number generator comprising a first shift register with p stages for storing and shifting a value with the least significant bit being adjacent an output terminal; a second shift register with b stages for storing and shifting a pre-loaded value with the least significant bit of the pre-loaded value being stored in the bth stage; a serial adder having at least l input taps with the serial adder adding the two values shifted out of the first and second shift registers and loading the sum output of the serial adder into the first shift register; and a controller for controlling clocking of the first and second shift registers and the serial adder, controlling pre-loading of the pre-load value into the second shift register, and clearing the serial adder.Type: GrantFiled: June 28, 1991Date of Patent: February 16, 1993Assignee: Digital Equipment CorporationInventor: Charles J. DeVane