Patents by Inventor Charles J. Hendricks

Charles J. Hendricks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7808257
    Abstract: A method and apparatus for the non-contact electrical test of both opens and shorts in electronic substrates. Top surface electrical test features are exposed to an ionization source under ambient conditions and the subsequent charge build up is measured as a drain current by probes contacting corresponding bottom surface features. Opens are detected by an absence of a drain current and shorts are detected by turning off the ionization source and re-measuring the bottom surface probes with a varying bias applied to each probe in the array.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: October 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: Christopher W. Cline, Edward J. Yarmchuk, Vincent A. Arena, Donald A. Merte, Thomas Picunko, Brian J. Wojszynski, Charles J. Hendricks, Michael E. Scaman, Robert S. Olyha, Jr., Arnold Halperin
  • Patent number: 6984997
    Abstract: A system and method for utilizing a multi-probe tester to test an electrical device having a plurality of contact pads. Multi-probe tester test probes and electrical device contact pads are arrayed in a common distribution pitch, wherein at least one test probe is masked, thereby preventing the at least one test probe from returning a test result to the testing apparatus. In one embodiment mask membrane physically prevents at least one test probe from making contact with the electrical device. In another embodiment at least one software command is provided configured to cause an input from at least one test probe to be disregarded during a test routine. Another embodiment features both mask membrane and software command probe masking.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Yuet-Ying Yu, Paul F. Bodenweber, Charles J. Hendricks, Frank C. Seelmann
  • Patent number: 6753688
    Abstract: A method and structure for an electronic circuit test and repair apparatus includes both of at least one wiring analyzer to locate circuit shorts and a current source to provide current sufficient to attempt to remove any identified shorts.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: June 22, 2004
    Assignee: International Business Machines Corporation
    Inventors: Roger M. Eddy, Charles J. Hendricks, Thomas Morrison, Robert N. Wiggin, Brian J. Wojszynski
  • Publication number: 20020145434
    Abstract: A method and structure for an electronic circuit test and repair apparatus includes both of at least one wiring analyzer to locate circuit shorts and a current source to provide current sufficient to attempt to remove any identified shorts.
    Type: Application
    Filed: April 10, 2001
    Publication date: October 10, 2002
    Applicant: International Business Machines Corporation
    Inventors: Roger M. Eddy, Charles J. Hendricks, Thomas Morrison, Robert N. Wiggin, Brian J. Wojszynski
  • Patent number: 6281692
    Abstract: Disclosed is an interposer and test structure for making contact between a substrate and a test bed. One embodiment of the interposer has a floating, rigid conductive element in a nonconductive body which makes temporary contact between the test bed and the substrate. In another embodiment of the invention, the interposer includes two layers of material, in which one layer includes pogo pins for contacting the substrate and the other layer includes pads for contacting the test bed. The pogo pins are on a grid spacing corresponding to that of the substrate input/output pads while the interposer pads are on a grid spacing corresponding to that of the pogo pin contactors of the test bed.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: August 28, 2001
    Assignee: International Business Machines Corporation
    Inventors: Paul F. Bodenweber, Ralph R. Comulada, Mukta S. Farooq, Charles J. Hendricks, Philo B. Hodge, Vincent P. Peterson, Terence W. Spoor, Kathleen M. Wiley, Yuet-Ying Yu
  • Patent number: 6235544
    Abstract: A multilayer thin film structure (MLTF) is provided having no extraneous via-pad connection strap plated metallurgy for defective vias needing removal. The method for making or repairing the MLTF comprises determining interconnection defects in the MLTF at a thin film layer adjacent to the top metal layer of the structure, applying a top surface dielectric layer and forming vias in the layer, applying a metal conducting layer and removing the metal conducting layer for via-pad connection straps of defective vias and at the intersection of XY lines used in the repair, defining the top surface metallization including a series of orthogonal X conductor repair lines and Y conductor repair lines using a photoresist and lithography and then using a phototool to selectively expose the photoresist to define top surface strap connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization using additive or subtractive metallization techniques.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: May 22, 2001
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Franklin, Charles J. Hendricks, Richard P. Surprenant, Stephen J. Tirch, III, Thomas A. Wassick, James P. Wood
  • Patent number: 6054863
    Abstract: A system for testing circuit boards comprising a probe network having a plurality of probes wherein each probe is adapted for contacting an end of a corresponding circuit board network and wherein each probe and network define a node having an address. The system further comprises a control device that includes a node address generator and a timing circuit having an output for outputting a pulse to the node having the address generated by the node address generator and for coupling the remaining nodes to electrical ground. The system further comprises a comparator for comparing the pulse outputted by the timing circuit to predetermined data.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: April 25, 2000
    Assignee: International Business Machines Corporation
    Inventors: Thomas Morrison, Siegfried Geyer, Charles J. Hendricks, Klaus Probst
  • Patent number: 4600464
    Abstract: An improved plasma reactor for uniformly etching a large number of semiconductor wafers at a reduced plasma potential includes, in one embodiment, a grounded plate mounted intermediate the cathode and the top plate of a reactor chamber, the top plate and the chamber walls forming the reactor anode. The grounded plate is spaced apart from the chamber top plate a distance sufficient to allow a plasma to be established between the grounded plate and the top plate, and the distance between the grounded plate and the cathode is large enough not to disturb the field in the proximity of the wafers being etched. The plate can be apertured to facilitate etchant gas flow. According to another embodiment of the invention at least two grounded plates are employed, spaced apart from each other and from the upper surface of the reactor plasma chamber.
    Type: Grant
    Filed: May 1, 1985
    Date of Patent: July 15, 1986
    Assignee: International Business Machines Corporation
    Inventors: Brian H. Desilets, Thomas A. Gunther, Charles J. Hendricks, John H. Keller
  • Patent number: 4534816
    Abstract: A high pressure, high etch rate single wafer plasma reactor having a fluid cooled upper electrode including a plurality of small diameter holes or passages therethrough to provide uniform reactive gas distribution over the surface of a wafer to be etched. A fluid cooled lower electrode is spaced from the upper electrode to provide an aspect ratio (wafer diameter: spacing) greater than about 25, and includes an insulating ring at its upper surface. The insulating ring protrudes above the exposed surface of the lower electrode to control the electrode spacing and to provide a plasma confinement region whereby substantially all of the RF power is dissipated by the wafer. A plurality of spaced apart, radially extending passages through the insulating ring provide a means of uniformly exhausting the reactive gas from the plasma confinement region.
    Type: Grant
    Filed: June 22, 1984
    Date of Patent: August 13, 1985
    Assignee: International Business Machines Corporation
    Inventors: Lee Chen, Charles J. Hendricks, Gangadhara S. Mathad, Stanley J. Poloncic
  • Patent number: 4340461
    Abstract: A plasma enhancing baffle plate is employed in conjunction with the anode of an RIE system to provide uniform silicon etching. The baffle plate is conductively coupled to and provided in relatively close proximity to the anode to form a constricted chamber region between anode and baffle plate. With the constricted chamber open to the RIE chamber through aperture means in the baffle plate the total surface area of the anode is increased, such that when the system is biased to operate in an RIE mode an increase in the generation of neutral etching species is effected. Various aperture arrangements may be employed to provide different patterns of neutral etching species generation, in accordance with the peculiar characteristics of the system employed.
    Type: Grant
    Filed: September 10, 1980
    Date of Patent: July 20, 1982
    Assignee: International Business Machines Corp.
    Inventors: Charles J. Hendricks, William W. Hicks, John H. Keller