Patents by Inventor Charles J. Holland

Charles J. Holland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5604862
    Abstract: An Integrity Server computer for economically protecting the data of a computer network's servers, and providing hot standby access to up-to-date copies of the data of a failed server. As the servers' files are created or modified, they are copied to the Integrity Server. The invention provides novel methods for managing the data stored on the Integrity Server, so that up-to-date snapshots of files of the protected file servers are stored on low-cost media such as tape, but without requiring that a system manager load large numbers of tapes.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: February 18, 1997
    Assignee: Network Integrity, Inc.
    Inventors: Christopher W. Midgely, Charles J. Holland, John W. Webb, Manuel Gonsalves
  • Patent number: 4679138
    Abstract: A data processing system in which macroinstructions are decoded to provide a sequence of microinstructions comprising one or more microroutines. A stack storage means stores data for use in such microroutines. The final microinstruction of the microroutines is a request to retrieve or remove data from the stack. When no data is present therein (the stack is empty) a new macroinstruction is requested and when data is present in the stack the microroutine returns to another mircoroutine in which it is acting as a micro-subsroutine to permit continuation of the other microroutine.
    Type: Grant
    Filed: April 23, 1981
    Date of Patent: July 7, 1987
    Assignee: Data General Corporation
    Inventors: David I. Epstein, Charles J. Holland
  • Patent number: 4554627
    Abstract: A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege.
    Type: Grant
    Filed: March 9, 1983
    Date of Patent: November 19, 1985
    Assignee: Data General Corporation
    Inventors: Charles J. Holland, Kenneth D. Holberger, David I. Epstein, Paul Reilly, Josh Rosen
  • Patent number: 4434459
    Abstract: A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded.
    Type: Grant
    Filed: April 25, 1980
    Date of Patent: February 28, 1984
    Assignee: Data General Corporation
    Inventors: Charles J. Holland, Steven Wallach, Carl J. Alsing
  • Patent number: 4386399
    Abstract: A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege.
    Type: Grant
    Filed: April 25, 1980
    Date of Patent: May 31, 1983
    Assignee: Data General Corporation
    Inventors: Edward Rasala, Steven Wallach, Carl J. Alsing, Kenneth D. Holberger, Charles J. Holland, Thomas West, James M. Guyer, Richard W. Coyle, Michael L. Ziegler, Michael B. Druke