Abstract: A self-timed circuit for use a clocked logic system is disclosed that comprises a timing detection device for detecting a timing margin of a critical path, the critical path being a path that limits the speed of the system. The circuit further comprises increase logic for increasing the speed of the system clock if the timing margin allows it, and decrease logic for decreasing the speed of the system clock if the timing margin indicates such a need. The increase and decrease logic comprise threshold generator and reset logic, and clock control logic.

Abstract: A circuit for delivering an accurate reference current independent of operating frequency that is implementable on-chip and that is relatively insensitive to process and temperature variations. A frequency source controls a rate of charge transfer via a switched capacitor to generate a constant current over different frequencies. A complimentary doped FET provides a band gap voltage imposed over a known resistance to generate the output current.

Abstract: A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.

Abstract: A current transition rate control circuit is provided, comprising first and second data inputs; first and second charge/discharge circuits for receiving the first and second data inputs; a first reference voltage circuit for sending a first control signal and a second reference voltage circuit for sending a second control signal to, respectively, the first and second charge/discharge circuits; and first and second output transistors coupled, respectively, to the outputs of the first and second charge/discharge circuits. The circuit controls the switching speed of the output transistors to minimize current spikes on the output. The circuit may include a pre-driver circuit for (i) receiving a single data input and outputting the first and second data inputs, and (ii) receiving a circuit disabling signal and placing the circuit in a high impedance state which turns off both of the output transistors.

Abstract: A voltage balancing circuit, particularly suitable for bipolar memory arrays producing small signals, is provided which includes first and second conductive lines, a point of reference potential, a first device disposed between the first conductive line and the point of reference potential, a second device disposed between the second conductive line and the point of reference potential, first and second transistors, first means for coupling the first line through the first transistor to the second line, second means for coupling the second line through the second transistor to the first line, and means for supplying substantially equal signals to the control electrodes of the first and second transistors. When used in a memory array, the conductive lines are the bit/sense lines, the point of reference potential is a bit/sense line reference voltage and the equal signals for the control electrodes of the transistors are provided in response to a signal from a bit decoder.

Abstract: A memory system is provided having an array of cells, each of which may include first and second cross-coupled inverting NPN transistors and first and second PNP transistors for injecting charge into the first and second inverting transistors. A first bit/sense line of a bit/sense line pair is connected to the emitter of the first inverting transistor and a second bit/sense line of the pair is connected to the emitter of the second inverting transistor and a common word line is connected to the emitters of the first and second charge injecting transistors. To read a selected cell, all cells of the array are discharged through the word lines, the pair of bit/sense lines connected to the selected cell are electrically floated or isolated and the word line connected to the selected cell is energized by a word driver. The signal developed in the bit/sense lines connected to the selected cell is detected while the word line connected to the selected cell is being energized by the word driver.

Abstract: A driver circuit charges a capacitive load to a voltage substantially equal to the voltage or potential of the power supply of the circuit by first charging the capacitive load with current flowing through a drive transistor under the control of the power supply potential and, thereafter, at a predetermined time charging the capacitive load under the control of a precharged bootstrap capacitor. The driver circuit includes a transistor, acting as a pull-up device, connected between the power supply and the capacitive load and a series circuit including a charge source and switching means connected between the capacitive load and a control gate of the transistor. The switching means is coupled to the capacitive load so as to be responsive to the voltage at the load for directing charge from the charge source into the pull-up transistor at a predetermined time to raise the voltage at the capacitive load to substantially the potential of the power supply.