Abstract: A microprocessor including a temperature sensor that monitors a temperature of core logic of the microprocessor during operation thereof, and operating point information from which may be determined N operating points at which the microprocessor core may reliably operate at a first temperature. Each of the N operating points has a different combination of operating frequency and voltage. The N operating points comprise a highest operating point, a lowest operating point, and a plurality of operating points intermediate the highest and lowest operating points. The microprocessor also includes a control circuit that transitions operation of the core logic among the N operating points to attempt to keep the operating temperature of the core logic provided by the temperature sensor within a temperature range whose upper bound is the first temperature.

Abstract: A microprocessor includes control hardware that receives and stores control values and provides the control values to circuits of the microprocessor for controlling operation of the microprocessor. The microprocessor also includes a first plurality of fuses selectively blown collectively with a predetermined value, and a second plurality of fuses selectively blown collectively with an error correction value computed from the predetermined value collectively blown into the first plurality of fuses. In response to being reset, the microprocessor reads the first and second plurality of fuses, detects an error in the value read from the first plurality of fuses using the value read from the second plurality of fuses, corrects the value read from the first plurality of fuses back to the predetermined value using the value read from the second plurality of fuses, and uses the corrected predetermined value to write the control values into the control hardware.

Abstract: A microprocessor including a temperature sensor that monitors a temperature of core logic of the microprocessor during operation thereof, and operating point information from which may be determined N operating points at which the microprocessor core may reliably operate at a first temperature. Each of the N operating points has a different combination of operating frequency and voltage. The N operating points comprise a highest operating point, a lowest operating point, and a plurality of operating points intermediate the highest and lowest operating points. The microprocessor also includes a control circuit that transitions operation of the core logic among the N operating points to attempt to keep the operating temperature of the core logic provided by the temperature sensor within a temperature range whose upper bound is the first temperature.

Abstract: A microprocessor control circuit continuously monitors core logic operating temperature and detects it has risen above a first temperature and responsively iteratively controls a system voltage source to output a next lower one of its N output voltage levels and controls clock generation circuitry of the microprocessor to output a lower one of its M core clock signal frequencies as necessitated by a transition to the next lower output voltage level until the temperature drops below the first temperature. The control circuit detects that the temperature has dropped below a second temperature and responsively iteratively controls the voltage source to output a next higher output voltage level and controls the clock generation circuitry to output a higher core clock signal frequency as permitted by the next higher output voltage level until the operating temperature rises above the second temperature. The M frequencies comprise a highest, lowest, and plurality of intermediate frequencies.

Abstract: A microprocessor includes control hardware that receives and stores control values and provides the control values to circuits of the microprocessor for controlling operation of the microprocessor. The microprocessor also includes a first plurality of fuses selectively blown collectively with a predetermined value, and a second plurality of fuses selectively blown collectively with an error correction value computed from the predetermined value collectively blown into the first plurality of fuses. In response to being reset, the microprocessor reads the first and second plurality of fuses, detects an error in the value read from the first plurality of fuses using the value read from the second plurality of fuses, corrects the value read from the first plurality of fuses back to the predetermined value using the value read from the second plurality of fuses, and uses the corrected predetermined value to write the control values into the control hardware.

Abstract: A power management controller for instantaneous frequency-based microprocessor power management including first and second PLLs, select logic, and source control logic. The first PLL generates a first core source clock signal at a first frequency based on a bus clock signal. The second PLL generates a second core source clock signal at a programmable frequency based on a frequency control signal and the bus clock signal. The select logic selects between the first and second core source clock signals to provide a core clock signal for the microprocessor based on a select signal. The source control logic detects power conditions via at least one power sense signal, provides the frequency control signal according to the power conditions, and provides the select signal. The power management controller enables transition from one power state to another in a single clock cycle, which is significantly faster than conventional power management techniques.