Abstract: A fabrication method for integrated circuits is disclosed wherein a structure is formed on one side of a supporting substrate which provides a ground plane with "X" wiring on one side and "Y" wiring on the other side thereof. The method includes a number of alternative initial planarization steps which permits the resulting device to be substantially planar, thereby allowing it to be used as a substrate for preparation of high density integrated circuits. A first planarization step includes the deposition of a niobium thin film on a doped silicon substrate; the delineation of the desired niobium "X" wiring pattern using well-known photolithographic and etching techniques, leaving the photoresist in place to protect the niobium; the anodization of exposed silicon substrate portions to form silicon dioxide surrounding the niobium to a higher level than the niobium; and the removal of the photoresist.