Patents by Inventor Charles Joseph Tabony
Charles Joseph Tabony has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10289412Abstract: Systems and methods for generating a floating point constant value from an instruction are disclosed. A first field of the instruction is decoded as a sign bit of the floating point constant value. A second field of the instruction is decoded to correspond to an exponent value of the floating point constant value. A third field of the instruction is decoded to correspond to the significand of the floating point constant value. The first field, the second field, and the third field are combined to form the floating point constant value. The exponent value may include a bias, and a bias constant may be added to the exponent value to compensate for the bias. The third field may comprise the most significant bits of the significand. Optionally, the second field and the third field may be shifted by first and second shift values respectively before they are combined to form the floating point constant value.Type: GrantFiled: February 9, 2012Date of Patent: May 14, 2019Assignee: QUALCOMM IncorporatedInventors: Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Swaminathan Balasubramanian
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Patent number: 10055227Abstract: Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.Type: GrantFiled: October 19, 2012Date of Patent: August 21, 2018Assignee: QUALCOMM IncorporatedInventors: Charles Joseph Tabony, Erich James Plondke, Lucian Codrescu, Suresh K. Venkumahanti, Evandro Carlos Menezes
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Patent number: 9678754Abstract: A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.Type: GrantFiled: March 3, 2010Date of Patent: June 13, 2017Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Erich James Plondke, Ajay Anant Ingle, Suresh K. Venkumahanti, Charles Joseph Tabony
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Patent number: 9116685Abstract: An apparatus includes a memory that stores an instruction including an opcode and an operand. The operand specifies an immediate value or a register indicator of a register storing the immediate value. The immediate value is usable to identify a function call address. The function call address is selectable from a plurality of function call addresses.Type: GrantFiled: July 19, 2011Date of Patent: August 25, 2015Assignee: QUALCOMM IncorporatedInventors: Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Ajay Anant Ingle, Suresh K. Venkumahanti, Evandro Carlos Menezes
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Patent number: 8990543Abstract: In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.Type: GrantFiled: March 11, 2008Date of Patent: March 24, 2015Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Robert Allan Lester, Charles Joseph Tabony, Erich James Plondke, Mao Zeng, Suresh Venkumahanti, Ajay Anant Ingle
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Patent number: 8843730Abstract: An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination.Type: GrantFiled: September 9, 2011Date of Patent: September 23, 2014Assignee: QUALCOMM IncorporatedInventors: Erich J. Plondke, Lucian Codrescu, Mao Zeng, Charles Joseph Tabony, Suresh K. Venkumahanti
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Publication number: 20130283023Abstract: Systems and methods for branch prediction, including predicting evaluation of a producer instruction such as a compare instruction, by encoding a prediction field in the producer instruction, and predicting evaluation of the producer instruction by using the encoded prediction field. A consumer instruction such as a conditional branch instruction predicated on the producer instruction can be speculatively executed based on the predicted evaluation of the producer instruction. The producer instruction is executed in an execution pipeline to determine an actual evaluation of the producer instruction, and the prediction field is updated, if necessary, based on the actual evaluation and the predicted evaluation. The producer instruction can be updated in memory with the updated prediction field.Type: ApplicationFiled: April 18, 2012Publication date: October 24, 2013Applicant: QUALCOMM INCORPORATEDInventors: Charles Joseph Tabony, Lucian Codrescu, Suresh K. Venkumahanti
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Publication number: 20130212357Abstract: Systems and methods for generating a floating point constant value from an instruction are disclosed. A first field of the instruction is decoded as a sign bit of the floating point constant value. A second field of the instruction is decoded to correspond to an exponent value of the floating point constant value. A third field of the instruction is decoded to correspond to the significand of the floating point constant value. The first field, the second field, and the third field are combined to form the floating point constant value. The exponent value may include a bias, and a bias constant may be added to the exponent value to compensate for the bias. The third field may comprise the most significant bits of the significand. Optionally, the second field and the third field may be shifted by first and second shift values respectively before they are combined to form the floating point constant value.Type: ApplicationFiled: February 9, 2012Publication date: August 15, 2013Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Swaminathan Balasubramanian
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Publication number: 20130024663Abstract: An apparatus includes a memory that stores an instruction including an opcode and an operand. The operand specifies an immediate value or a register indicator of a register storing the immediate value. The immediate value is usable to identify a function call address. The function call address is selectable from a plurality of function call addresses.Type: ApplicationFiled: July 19, 2011Publication date: January 24, 2013Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Ajay Anant Ingle, Suresh K. Venkumahanti, Evandro Carlos Menezes
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Publication number: 20120284489Abstract: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.Type: ApplicationFiled: June 8, 2011Publication date: November 8, 2012Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Suresh K. Venkumahanti, Ajay Anant Ingle
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Publication number: 20120284488Abstract: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.Type: ApplicationFiled: May 3, 2011Publication date: November 8, 2012Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Suresh K. Venkumahanti, Ajay Anant Ingle
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Publication number: 20110219212Abstract: A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.Type: ApplicationFiled: March 3, 2010Publication date: September 8, 2011Applicant: QUALCOMM INCORPORATEDInventors: Lucian Codrescu, Erich James Plondke, Ajay Anant Ingle, Suresh K. Venkumahanti, Charles Joseph Tabony
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Publication number: 20110125987Abstract: A dedicated arithmetic decoding instruction is disclosed. In a particular embodiment, an apparatus includes a memory and a processor coupled to the memory. The processor is configured to execute general purpose instructions and to execute a dedicated arithmetic decoding instruction retrieved from the memory.Type: ApplicationFiled: November 20, 2009Publication date: May 26, 2011Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Lucian Codrescu, Ajay Anant Ingle, Mao Zeng, Christopher Edward Koob, Charles Joseph Tabony
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Publication number: 20090235051Abstract: In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.Type: ApplicationFiled: March 11, 2008Publication date: September 17, 2009Applicant: QUALCOMM INCORPORATEDInventors: Lucian Codrescu, Robert Allan Lester, Charles Joseph Tabony, Erich James Plondke, Mao Zeng, Suresh Venkumahanti, Ajay Anant Ingle