Patents by Inventor Charles K. Wallace

Charles K. Wallace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154037
    Abstract: Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 9, 2024
    Inventors: Leonard P. GULER, Tahir GHANI, Charles H. WALLACE, Mohit K. HARAN, Mohammad HASAN, Aryan NAVABI-SHIRAZI, Allen B. GARDINER
  • Patent number: 11972979
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Michael Harper, Suzanne S. Rich, Charles H. Wallace, Curtis Ward, Richard E. Schenker, Paul Nyhus, Mohit K. Haran, Reken Patel, Swaminathan Sivakumar
  • Publication number: 20240113177
    Abstract: An integrated circuit includes a first device having a first source or drain region, and a second device having a second source or drain region that is laterally adjacent to the first source or drain region. A conductive source or drain contact includes (i) a lower portion in contact with the first source or drain region, and extending above the first source or drain region, and (ii) an upper portion extending laterally from above the lower portion to above the second source or drain region. A dielectric material is between at least a section of the upper portion of the conductive source or drain contact and the second source or drain region. In an example, each of the first and second devices is a gate-all-around (GAA) device having one or more nanoribbons, nanowires, or nanosheets as channel regions, or is a finFet structure having a fin-based channel region.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Sukru Yemenicioglu, Quan Shi, Marni Nabors, Charles H. Wallace, Xinning Wang, Tahir Ghani, Andy Chih-Hung Wei, Mohit K. Haran, Leonard P. Guler, Sivakumar Venkataraman, Reken Patel, Richard Schenker
  • Publication number: 20240113019
    Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines in a first inter-layer dielectric (ILD) layer, the plurality of conductive lines on a same level and along a same direction. A second ILD layer is over the plurality of conductive lines and over the first ILD layer. A first conductive via is in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines, the first conductive via having a straight edge.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Leonard P. GULER, Mohit K. HARAN, Nikhil MEHTA, Charles H. WALLACE, Tahir GHANI, Sukru YEMENICIOGLU
  • Publication number: 20240105716
    Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Inventors: Leonard P. GULER, Sukru YEMENICIOGLU, Mohit K. HARAN, Stephen M. CEA, Charles H. WALLACE, Tahir GHANI, Shengsi LIU, Saurabh ACHARYA, Thomas O'BRIEN, Nidhi KHANDELWAL, Marie T. CONTE, Prabhjot LUTHRA
  • Patent number: 4743876
    Abstract: A circuit breaker characterized by a voltage-responsive device having an electromagnet including an armature. A linkage connects the armature to the trip latch of the circuit breaker in order to open the circuit breaker contacts when a voltage occurs that is less than a predetermined voltage value. Under normal operating conditions, when the contacts are closed, the armature is retained in place by an electromagnetic force, but is biased away therefrom when the voltage drops below that voltage value.
    Type: Grant
    Filed: July 24, 1987
    Date of Patent: May 10, 1988
    Assignee: Westinghouse Electric Corp.
    Inventors: Stanislaw A. Milianowicz, Charles K. Wallace
  • Patent number: 4491704
    Abstract: There is provided by this invention a vacuum monitoring device for use in vacuum circuit interrupters comprising a stacked resistor assembly as a voltage divider coupled to an internal shield of the vacuum bottle and a low voltage detection circuit for monitoring leakage currents under abnormal pressure conditions.
    Type: Grant
    Filed: April 25, 1983
    Date of Patent: January 1, 1985
    Assignee: Westinghouse Electric Corp.
    Inventors: Stanislaw A. Milianowicz, Norman Davies, Charles K. Wallace