Abstract: A data processing system (10) provides flexibility in interfacing with both a variety of memory devices (56, 58) and external peripheral devices (58). A control register (94) is provided for dynamically controlling a timing relationship between read and write accesses executed by the data processing system. A first set of bits (WP) stored in the control register determines an amount of time a write enable signal is asserted to indicate a length of time required to write a data value to an external device. By recognizing the difference in the timing requirements for read and write operations among different external peripheral devices and memories, as well as the difference in the timing requirements of read and write operations on the same external device, the first set of bits of the control register uses the best timing scheme available to increase the efficiency of the data processing system.

Abstract: A data processing system (10) flexibly interfaces with both a variety of memory devices and external peripheral devices. A control register (94) is provided for dynamically controlling a timing relationship for read and write accesses executed by the system. A first set of bits (PA) in the control register provides timing control for an initial amount of time required to read a first data value from an external device. A second set of bits (SA) in the control register provides timing control for each successive amount of time required to read a successive data value from the external device.