Abstract: An optical lens structure includes a substantially transparent substrate a lens array attached to the substrate with lenses of the lens array situated opposite the substrate and packaging material surrounding at least the periphery of the lens array, the packaging material including at least two alignment holes which are aligned with respect to positions of the lenses. In one example, the structure is fabricated by attaching a lens array to a substrate with lenses of the lens array situated opposite the substrate, surrounding a periphery of the lens array with a packaging material, the packaging material being attached to the substrate, planarizing the packaging material, and providing alignment holes through the packaging material.

Abstract: A method of positioning an optoelectronic device, for example a vertical cavity surface emitting laser, onto an optical fiber connector and maintaining that exact alignment while testing the quality of the optical output prior to applying an adhesive to make the interface permanent. The method includes the utilization of a multi-piece fixture which clamps the elements into position, allows for testing, and provides a fixture to maintain position throughout the curing process.

Abstract: A method of positioning an optoelectronic device, for example a vertical cavity surface emitting laser, onto an optical fiber connector and maintaining that exact alignment while testing the quality of the optical output prior to applying an adhesive to make the interface permanent. The method includes the utilization of a multi-piece fixture which clamps the elements into position, allows for testing, and provides a fixture to maintain position throughout the curing process.

Abstract: Scalable Computer Interconnect (CSI) compliant multi-stage switching networks compactly electrically communicatively interconnect a large number N of electrically communicating devices, typically computers or memories, in three-dimensional space. The logic networks, including a preferred “layered network” of U.S. Pat. No. 4,833,468, are (i) rotated, (ii) folded and (iii) squared per companion U.S. Pat. No. 6,301,247 so as to assume optimal topology. The topologically-optimized switching network logic is physically realized as (i) planar panels each mounting multi-chip modules, or tiles, each having logic switchpoints each realized by switch dice, plus vias through the tiles, plus pads upon both sides of the tiles, plus connective wiring layers upon the tile, connected by (ii) multi-conductor flexible flat printed circuit cables located between the adjacent panels. System peak performance is 24 teraflops/second.

Abstract: Dense physical and electrical connection of (i) flat flexible multiconductor cables of the printed circuit or ribbon types, to (ii) to spaced-parallel planar modules, particularly to switching modules containing switching chips, is realized by (1) a particular connection geometry in combination with (2) a spring clip connector. Flat flexible multiconductor cables routed through free space either in (i) “X” and, optionally also, “Z” planes, or else in (ii) “Y” planes exclusively, have their conductors' ends stripped and bent 90° so as to lie upon conductive pads, arrayed along lines angled 45° to both the “X” and “Y” planes, located on the substrates of switching modules that are within “Z” planes.