Patents by Inventor Charles Kwok-Wah Lo

Charles Kwok-Wah Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Heterogeneous multiprocessor platform targeting programmable integrated circuits
    Patent number: 9846660
    Abstract: An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: December 19, 2017
    Assignee: XILINX, INC.
    Inventors: Henry E. Styles, Jeffrey M. Fifield, Ralph D. Wittig, Philip B. James-Roxby, Sonal Santan, Devadas Varma, Fernando J. Martinez Vallina, Sheng Zhou, Charles Kwok-Wah Lo
  • HETEROGENEOUS MULTIPROCESSOR PLATFORM TARGETING PROGRAMMABLE INTEGRATED CIRCUITS
    Publication number: 20160132441
    Abstract: An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 12, 2016
    Inventors: Henry E. Styles, Jeffrey M. Fifield, Ralph D. Wittig, Philip B. James-Roxby, Sonal Santan, Devadas Varma, Fernando J. Martinez Vallina, Sheng Zhou, Charles Kwok-Wah Lo