Abstract: A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom.

Abstract: A data transmission system includes parallel data paths for transmitting data, and an encoder for encoding the data such that an error correction code is generated for data at a same bit position across the parallel data paths.

Abstract: A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom.

Abstract: A method and apparatus in accordance with the present invention provides monitoring a self-adjusting multi-tier processing system. At least one computing resource of one of the tiers of the self-adjusting multi-tier processing system is dynamically bypassed based on at least one predetermined criterion, wherein dynamically bypassing energizes or de-energizes a bypass control switch that operates to route data between tiers of the system in a manner that excludes the at least one computing resource.

Abstract: A method and apparatus in accordance with the present invention provides monitoring a self-adjusting multi-tier processing system. At least one computing resource of one of the tiers of the self-adjusting multi-tier processing system is dynamically bypassed based on at least one predetermined criterion, wherein dynamically bypassing energizes or de-energizes a bypass control switch that operates to route data between tiers of the system in a manner that excludes the at least one computing resource.

Abstract: A data transmission system includes parallel data paths for transmitting data, and an encoder for encoding the data such that an error correction code is generated for data at a same bit position across the parallel data paths.

Abstract: An apparatus for data transfer using radio frequency (RF) energy, includes a first software application that sources and links the data transfer, a second software application for controlling a communications hardware for the data transfer, a hardware device for formatting the data and gaining access to a media, and a physical layer interface hardware, coupled to selectively receive a signal representing the data from the hardware device and to provide an output to the hardware device, for sending and receiving a radio frequency communication. The second software application for controlling the communications hardware uses a target data transmission media of infrared light.

Abstract: A format converter in which the data input is a 16 bit wide interface. The circuit finds the 66-bit coding block boundaries. In one embodiment, a circuit presents the 66-bit data blocks at the output in an aligned format. The circuit relies on control inputs from a state machine which controls the operating mode and to which it delivers status information. The two main operating modes are the “normal data” mode or the “hunt” mode for the 66-bit block boundaries.

Abstract: A network port configurator device for automatically configuring a system having network workstations and corresponding network equipment of various physical protocols. The network port configurator comprises a plurality of input and output ports for receiving physical wiring to which the workstations and network equipment are attached. Detection circuitry attached to the input and output ports determine the physical protocol of the attached workstations and network equipment by determining a characteristic of the attached equipment. Examples of identifying characteristics include a characteristic impedance, a characteristic voltage, and a characteristic cable identification of the workstation. Logic circuitry uses this information to control a circuit switching mechanism that connects the input ports to the output ports.