Abstract: The specification discloses a package for a large number of integrated circuits. The package includes a top piece and a bottom piece formed of crystalline silicon with two levels of conductor regions formed in the top and bottom pieces. The integrated circuits are placed vertically between the top and bottom pieces and are held to the top and bottom pieces by high temperature adhesives. Solder balls which are placed on integrated circuits after the fabrication of the integrated circuits are then heated to cause the solder balls to reflow onto their respective connectors in the top and bottom pieces. TAB type conductors are then connected to the top and bottom pieces so that the integrated circuit held within this embodiment of the present invention may be connected to other circuitry.

Abstract: The specification discloses a package for a large number of integrated circuits. The package includes a top piece and a bottom piece formed of crystalline silicon with two levels of conductor regions formed in the top and bottom pieces. The integrated circuits are placed vertically between the top and bottom pieces and are held to the top and bottom pieces by high temperature adhesives. Solder balls which are placed on integrated circuits after the fabrication of the integrated circuits are then heated to cause the solder balls to reflow onto their respective connectors in the top and bottom pieces. TAB type conductors are then connected to the top and bottom pieces so that the integrated circuit held within this embodiment of the present invention may be connected to other circuitry.

Abstract: A reconfigurable circuit operating in a test mode and a normal operating mode includes a memory array (10) which has a row decoder (12) for addressing the memory elements therein. The row decoder (12) has a fused switch (18) for referencing the output circuits thereon to either a standard reference voltage or an external reference voltage. The memory array (10) has a fused switch (22) associated therewith for referencing the charging voltage for the memory cells to either the positive reference voltage in the circuit or to an external variable voltage. The fused switches (18) and (22) are operable to switch to internal references for the normal operating mode and to the external variable voltages for the test mode.

Abstract: A memory device is described which has the capability for testing portions of its circuitry with a variable test voltage, while allowing the remainder of the circuit to not be affected by variations in the test voltage. A specific example of a test utilizing this feature is a test directed to the leakage of stored charge in a dynamic memory cell through its access transistors controlled by the row lines. A circuit is disclosed which connects a test voltage terminal through a first fuse to the node to which the row decoder biases the unselected row lines. A second fuse and associated circuitry decouples the normal reference supply from this particular node, but does not affect the presence of the reference supply elsewhere in the memory device. The voltage of the test voltage terminal may be modulated to determine the voltage at which the access transistors in the array cause stored charge to leak during a memory cycle which selects another row in the array.