Abstract: A single synchronous system bus interconnecting a number of distributed processors which emulate multiple channels of a multichannel system. The system uses multichannel software and each channel is distributed among all of the distributed processors. The bus provides for communication among the distributed processors and a memory controller. One of the distributed processors accepts and converts multichannel software and transmits formatted words on the system bus and another of the distributed processor stores the instruction received in the formatted words. The first processor, thereby, acquires control over the system bus and the second processor, as slave, processes the instruction received in accordance with its microde programming, generates data transfer control signals and transmits formatted words via the system bus destined for a distributed processor or main memory controller.

Abstract: A controller for at least one secondary storage device for use in a data processing system having a system bus which accommodates a device or a CPU that first acquires control, a device bus that has the same address, data and control format as the system bus and a cache bus which maintains its own timing for address and data signals. The controller has means for transferring the control signals between the device bus and the system bus to establish control over the system bus by the secondary storage device. The data, address and control signals are transferred between the device bus and the cache bus in accordance with the cache bus timing.

Abstract: An address recall system coupled to a processor to permit operator examination of a predetermined number of executed system addresses. A processor system address is manually inserted to the recall system. When a system address being executed compares with the operator address setting, an address equality signal is generated. The recall system logic generates either a stop or interrupt state for the processor responsive to actuation of another manually operated input switch. Addresses being executed by the processor are stored in a push down memory stack within the recall system. When an address equality signal is generated, one or more of the consecutively executed addresses contained in the memory stack may be manually displayed in the reverse order of execution.