Abstract: A high speed sigma-delta A/D converter for a sequence of analog samples xn (n=0,1,2, . . . N−1) has an input, a plurality N−1 of phase clocks &PHgr;n, a plurality of sample-hold circuits 40n, a plurality N−1 of circuit stages, and a D/A converter. The input receives the analog samples xn. The sample-hold circuits 40n are coupled to the input and each responds to a respective phase clock &PHgr;n to sample and hold a corresponding analog sample Xn. Each circuit stage n has a summer 42n and a quantizer 44n. The summer has (i) a data input receiving a data signal (xn) from a corresponding sample-hold circuit 40n, (ii) a prior sum signal (wn−1) input, and (iii) a prior quantized signal (yn−1) negative input. The summer 42n produces a sum signal (wn=xn+wn−−Yn−1) at a summer output. The quantizer 44n is coupled to the summer's output for quantizing the sum signal wn into a quantized sum signal yn.