Abstract: An escape outline is provided to automatically identify escape traces of a breakout. Further, the escape outline can be used to associate desired properties with the identified escape traces and allows special behavior of the automatic and interactive routing routines that operate on the escapes. Still further, an escape outline may be employed to improve the creation of escape traces by automatic routing tools. The use of pseudo-pins for netline optimization also is provided. Breakouts in a printed circuit board design are analyzed, and their respective endpoints are identified. These endpoints are then employed in a netline optimization analysis instead of the pins from which the breakouts originate. In this manner, the endpoints of the breakout are used as pseudo-pins to substitute for the actual pins of a component.

Abstract: Methods and apparatuses for routing traces in a layout design, such as for example a layout design for an integrated circuit, are disclosed. In various implementations, a group of netlines within a layout design and a freeform sketch are identified. Subsequently, the netlines are routed as traces according to the freeform sketch. More particularly, the geometry of the traces is determined by approximating the geometry of the freeform sketch. Various implementations of the invention provide for the netlines to be routed by an automated trace routing engine. With further implementations of the invention, ball grid array escapes and trace fanouts are additionally routed. For example, ball grid array escapes may be routed prior to netlines being routed according to the freeform sketch. In further implementations of the invention, the freeform sketch is deleted after the traces have been routed.

Abstract: A server computer maintains a master database for a PCB design, and a copy of the PCB design is provided to multiple client computers. The server assigns each client a different pair of pins for which a connection must be routed. When a client completes an assigned routing task, it requests that the server update the PCB master design with the route found by the client for its assigned pin pair. After forwarding the request, the client does not update its copy of the PCB design to reflect the found route. Instead, the client returns its copy to the state occupied prior to assignment of the pin pair by the server. Upon receiving notification that the server incorporated the found route, the client updates its copy of the design to include that route.

Abstract: Various techniques are disclosed for identifying different fanout via configurations that can be created using fanout vias, and then arranging those fanout via configurations in an alternating manner in order to increase the amount and/or area of routing channels available to route traces to the fanout vias. According to some of these techniques, a first fanout via configuration is selected, which can connect a component pin to a first layer of a multilayer printed circuit board. Next, a second fanout via configuration is selected, which can connect a component pin to a second layer of a multilayer printed circuit board different from the first layer. When the printed circuit board is designed, lines of these vias configurations are formed to correspond to a component that will be mounted on the printed circuit board. Each line will have a series of the first fanout via configuration alternating with a series of the second fanout via configuration.

Abstract: Multiple users may simultaneously edit a shared area of a printed circuit board design. In order to prevent conflicts between multiple users, a user draws a protection border around a portion of his or her workspace so as to temporarily reserve the protected portion and prevent editing by other users. The protection border may be broadcast to other users. The protection border may also define a protected region in which a user may evaluate alternative design changes without requesting corresponding changes to a master PCB design.

Abstract: Multiple users simultaneously edit at least a portion of a printed circuit board (PCB) design. The PCB design portion is transmitted to first and second clients for graphical display at each of the clients. A first protection boundary is associated with an area of the PCB design being edited at the first client. A second protection boundary is associated with an area of the PCB design being edited at the second client. The first and second protection boundaries are displayed at each of the first and second clients. A request from one of the clients to edit an object within a region bounded by a protection boundary associated with the other client is rejected. The protection boundary may surround a user's cursor. The size of the boundary may increase based on editing activity by a user in an area of a PCB design.

Abstract: Various techniques are disclosed for identifying different fanout via configurations that can be created using fanout vias, and then arranging those fanout via configurations in an alternating manner in order to increase the amount and/or area of routing channels available to route traces to the fanout vias. According to some of these techniques, a first fanout via configuration is selected, which can connect a component pin to a first layer of a multilayer printed circuit board. Next, a second fanout via configuration is selected, which can connect a component pin to a second layer of a multilayer printed circuit board different from the first layer. When the printed circuit board is designed, lines of these vias configurations are formed to correspond to a component that will be mounted on the printed circuit board. Each line will have a series of the first fanout via configuration alternating with a series of the second fanout via configuration.

Abstract: An escape outline is provided to automatically identify escape traces of a breakout. Further, the escape outline can be used to associate desired properties with the identified escape traces and allows special behavior of the automatic and interactive routing routines that operate on the escapes. Still further, an escape outline may be employed to improve the creation of escape traces by automatic routing tools. The use of pseudo-pins for netline optimization also is provided. Breakouts in a printed circuit board design are analyzed, and their respective endpoints are identified. These endpoints are then employed in a netline optimization analysis instead of the pins from which the breakouts originate. In this manner, the endpoints of the breakout are used as pseudo-pins to substitute for the actual pins of a component.

Abstract: A server computer maintains a master database for a PCB design, and a copy of the PCB design is provided to multiple client computers. The server assigns each client a different pair of pins for which a connection must be routed. When a client completes an assigned routing task, it requests that the server update the PCB master design with the route found by the client for its assigned pin pair. After forwarding the request, the client does not update its copy of the PCB design to reflect the found route. Instead, the client returns its copy to the state occupied prior to assignment of the pin pair by the server. Upon receiving notification that the server incorporated the found route, the client updates its copy of the design to include that route.

Abstract: Multiple users may simultaneously edit a shared area of a printed circuit board design. In order to prevent conflicts between multiple users, a user draws a protection border around a portion of his or her workspace so as to temporarily reserve the protected portion and prevent editing by other users. The protection border may be broadcast to other users. The protection border may also define a protected region in which a user may evaluate alternative design changes without requesting corresponding changes to a master PCB design.