Abstract: A flash memory system for an A/V player, utilizing a two-level round-robin write scheme upon N flash memory planes, enabling the A/V player to be loaded with data at a data throughput essentially N times the write throughput of one of the flash memory planes. The flash chips' memory cores and data registers, and the memory system's write buffers, can be kept fully utilized during data writing.

Abstract: A flash memory system for an A/V player, utilizing a two-level round-robin write scheme upon N flash memory planes, enabling the A/V player to be loaded with data at a data throughput essentially N times the write throughput of one of the flash memory planes. The flash chips' memory cores and data registers, and the memory system's write buffers, can be kept fully utilized during data writing.

Abstract: Multiple views of the signal are generated by a time-sharing use of the oscilloscope's acquisition hardware. The instrument software makes a set of measurements of the input signal, and from the results of those measurements classifies the input signal as to type. Signals of particular types implicitly select suites of views of the signal. The operator sees examples of the other views available while a related view is the main view. Alternate views can be “live” miniature views, and displayed alongside in simplified form, alongside the main view. By clicking on them, these alternative views may be made to become the main view. The operator can add and modify views. Each view comes with a set of measurements that are automatically performed and the results are displayed on the screen as text annotation to the waveform. A different view of the signal comes with different automatic measurements, and presents the results of these measurements as annotations to the waveform image.

Abstract: An improved sub-range ADC uses a sigma delta converter which eliminates both the sample and hold and digital-to-analog converter circuits of prior sub-ranging ADCs. An input analog signal is applied to a sigma delta modulator that provides a one-bit output. The one-bit output is input to a first analog filter and a digital correction circuit. The output from the first analog filter and the input analog signal, suitably delayed and optionally filtered, are input to a difference amplifier that provides the input to an ADC. The output of the ADC also is input to the digital correction circuit. The digital correction circuit includes a digital decimation filter for the one-bit sigma delta modulator output to produce a multi-bit digital output that is added to, the output from the ADC. The resulting digital signal may be additionally digitally filtered to produce a converted digital signal that corresponds to the input analog signal.

Abstract: A simplified user interface for an electronic test and measurement device comprises an arrangement of a segmented LCD device and a plurality of keys used to implement a softkey system, in combination with a single AMPs input connector and a rotary selector having only a single position for each basic kind of parameter to be measured. The segmented LCD device includes, at each location adjacent to a key, a plurality of segments representing a vertically-arranged list of functions to be controlled. In one embodiment of the invention, the housing of the electronic test and measurement device is fabricated to have finger-like projections overlaying a portion of the LCD screen for creating the appearance of the continuation of displayed LCD softkey separation lines.

Abstract: A method and apparatus for measuring the RMS value of an electrical signal. An electrical signal is converted to a digital signal. The digital signal is squared and low pass filtered to extract the DC component, the DC component being recognized as the mean-square of the signal. In use in a measurement device, the square root of the DC component is taken and displayed as the RMS value of the electrical signal.

Abstract: A high-speed data acquisition and processing system. The system includes a sequential sampler that samples an input signal at periodic intervals. The resulting samples are provided on a plurality of sample outputs. These sample outputs are received by a matrix of signal processors, each of which receives and processes at least two inputs, and provides a processor output. The first row of signal processors receives the sample outputs and processes them. Subsequent rows of signal processors receive and process the outputs of signal processors in previous rows.

Abstract: An analog acquisition system includes an array of analog capture cells for capturing and storing a signal on an analog bus. Each capture cell in the array may be sequentially selected for sampling the signal at successive sample times. Timing for selecting a row of the analog memory array is provided by a slow shift register and timing for selecting a capture cell within the row of the analog memory array is provided by a fast tapped delay line. Additional circuitry is provided for controlling the delay of the tapped delay line such that total delay is equal to the time the slow shift register takes to transfer from one row to the next.

Abstract: An adaptive filtering procedure reduces overshoot which may be present on a waveform having infinite slopes displayed on a digital oscilloscope as a result of interpolation between samples at the location of the infinite slopes. An adaptive filtering procedure identifies sampled points adjacent the infinite slope and moves the points closer to each other to avoid ringing or overshoot on the display. Before modification, a straightness test relative to the waveform before and after a discontinuity and a test for sudden changes in the waveform before and after the discontinuity are performed.

Abstract: A loop control system for digital processing apparatus. A dedicated storage register and associated counting register are provided for receiving a starting value representing a number of passes through a program loop. An iteration circuit is provided for receiving the value in the counting register, iterating it, and storing the new value in the same counting register with each successive pass through the loop. A detector is provided for comparing the output of the iteration circuit to a predetermined value and providing a completion signal when the new value and the ending value have a predetermined relative relationship. Control logic is provided for causing the value in the storage register to be transferred into the counting register upon the occurrence of an output signal from the detector circuit. A plurality of pairs of storage and counting registers may be provided for keeping track of the number of iterations of nested loops.

Abstract: An address computation system for updating starting addresses of data arrays in an array processor within an instruction cycle. A first set of registers is provided for storing starting addresses for each array. A second set of registers is provided for storing current addresses for each array. Logic is provided for initially providing, at the beginning of a series of computation steps to be executed repetitively, an address from a register in the first set of registers, changing that address, and storing it back in the same register and in a corresponding register in the second set, thereby updating the starting address for the next repetition of those computational steps while advancing the current address to the second of those steps.

Abstract: A digital oscilloscope provides sine interpolation between sampled data points and includes means for intensifying the cathode-ray-tube display to emphasize portions of the cathode-ray-tube trace corresponding to original samples while deemphasizing portions of the trace representing interpolated information.

Abstract: A digital storage oscilloscope is provided with an anti-aliasing filter circuit utilizing a first plurality of switchable analog filters that bandwidth limit frequencies greater than half the oscilloscope's sampling frequency, and a digital transversal filter effective at lower sweep rates and sampling rates for also bandwidth limiting frequencies greater than half the sampling frequency. The digital transversal filter is controllable to provide a different band pass characteristic for different sweep and sample rates. Both the selection of filters and the control of the digital filter are responsive to the oscilloscope's selection of sweep rate.

Abstract: A high-speed acquisition system employing an analog memory matrix is provided in which sample-hold elements connected to an analog bus are arranged in rows and columns to form an M.times.N matrix. The system is operable in a fast in-slow out mode, and the analog memory matrix may be implemented on a single integrated-circuit semiconductor chip.