Abstract: A capacitor in a semiconductor integrated circuit is fabricated having a fixed charge density introduced near an electrode/dielectric interface. The fixed charge density compensates for the effects of a depletion layer, which would otherwise lower the effective capacitance. By shifting the undesirable effect of the depletion capacitance outside of the operating voltage range, the capacitor is effectively converted to an accumulation mode. The fixed charge density is preferably introduced by a plasma nitridation process performed prior to formnation of the capacitor dielectric.

Abstract: A capacitor in a semiconductor integrated circuit is fabricated having a fixed charge density introduced near an electrode/dielectric interface. The fixed charge density compensates for the effects of a depletion layer, which would otherwise lower the effective capacitance. By shifting the undesirable effect of the depletion capacitance outside of the operating voltage range, the capacitor is effectively converted to an accumulation mode. The fixed charge density is preferably introduced by a plasma nitridation process performed prior to formation of the capacitor dielectric.

Abstract: A capacitor in a semiconductor integrated circuit is fabricated having a fixed charge density introduced near an electrode/dielectric interface. The fixed charge density compensates for the effects of a depletion layer, which would otherwise lower the effective capacitance. By shifting the undesirable effect of the depletion capacitance outside of the operating voltage range, the capacitor is effectively converted to an accumulation mode. The fixed charge density is preferably introduced by a plasma nitridation process performed prior to formation of the capacitor dielectric.

Abstract: A capacitor in a semiconductor integrated circuit is fabricated having a fixed charge density introduced near an electrode/dielectric interface. The fixed charge density compensates for the effects of a depletion layer, which would otherwise lower the effective capacitance. By shifting the undesirable effect of the depletion capacitance outside of the operating voltage range, the capacitor is effectively converted to an accumulation mode. The fixed charge density is preferably introduced by a plasma nitridation process performed prior to formation of the capacitor dielectric.

Abstract: A semiconductor processing method of providing a polysilicon layer atop a semiconductor wafer comprises the following sequential steps: a) depositing a first layer of arsenic atop a semiconductor wafer; b) depositing a second layer of silicon over the arsenic layer, the second layer having an outer surface; c) first annealing the wafer at a temperature of at least about 600.degree. C. for a time period sufficient to impart growth of polycrystalline silicon grains in the second layer and providing a predominately polysilicon second layer, the first annealing step imparting diffusion of arsenic within the second layer to promote growth of large polysilicon grains; and d) with the second layer outer surface being outwardly exposed, second annealing the wafer at a temperature effectively higher than the first annealing temperature for a time period sufficient to outgas arsenic from the polysilicon layer.

Abstract: A method (50) for designing a semiconductor device (10). The method (50) has an annealing step (59). In the annealing step (59), the semiconductor device (10) is annealed in an ambient containing oxygen. The oxygen has a partial pressure of greater than 11.85 Torr. The annealing step (59) results in a reduction of uncontrolled doping from the gate electrode (33) of the semiconductor device (10) to the channel region of the semiconductor device (10).

Abstract: A capacitor in a semiconductor integrated circuit is fabricated having a fixed charge density introduced near an electrode/dielectric interface. The fixed charge density compensates for the effects of a depletion layer, which would otherwise lower the effective capacitance. By shifting the undesirable effect of the depletion capacitance outside of the operating voltage range, the capacitor is effectively converted to an accumulation mode. The fixed charge density is preferably introduced by a plasma nitridation process performed prior to formation of the capacitor dielectric.

Abstract: A semiconductor processing method of providing a polysilicon layer atop a semiconductor wafer comprises the following sequential steps: a) depositing a first layer of arsenic atop a semiconductor wafer; b) depositing a second layer of silicon over the arsenic layer, the second layer having an outer surface; c) first annealing the wafer at a temperature of at least about 600.degree. C. for a time period sufficient to impart growth of polycrystalline silicon grains in the second layer and providing a predominately polysilicon second layer, the first annealing step imparting diffusion of arsenic within the second layer to promote growth of large polysilicon grains; and d) with the second layer outer surface being outwardly exposed, second annealing the wafer at a temperature effectively higher than the first annealing temperature for a time period sufficient to outgas arsenic from the polysilicon layer.

Abstract: A semiconductor processing method of providing a polysilicon layer atop a semiconductor wafer comprises the following sequential steps: a) depositing a first layer of arsenic atop a semiconductor wafer; b) depositing a second layer of silicon over the arsenic layer, the second layer having an outer surface; c) first annealing the wafer at a temperature of at least about 600.degree. C. for a time period sufficient to impart growth of polycrystalline silicon grains in the second layer and providing a predominately polysilicon second layer, the first annealing step imparting diffusion of arsenic within the second layer to promote growth of large polysilicon grains; and d) with the second layer outer surface being outwardly exposed, second annealing the wafer at a temperature effectively higher than the first annealing temperature for a time period sufficient to outgas arsenic from the polysilicon layer.

Abstract: There is a slotted cantilever diffusion tube system with a temperature insulating baffle system and a distributed gas injector system. Uniquely, there is an enhanced system that decreases the defects of wafers due to temperature, pressure, and concentration fluctuations in a low pressure chemical vapor deposition (LPCVD) process for fabricating IC wafers. Specifically, there is a cantilevered diffusion quartz tube system (12, 14) that has at least one temperature and pressure barrier baffle (28) placed between the lower temperature end (27) of the tube and the wafers under process (18). Additionally, there are at least two deposition gas injection exhaust ports (30, 32, 34) distributed along the length of the quartz tube near the wafers to assure that there is a relatively uniform concentration of diffusion gas in the heating chamber (17).

Abstract: An LPCVD deposition process for depositing doped thin films on a substrate is provided. The process may be performed in a LPCVD reaction chamber at elevated temperatures and reduced pressures. The process is especially suited to the deposition and doping of chemically incompatible deposition species and dopants such as polysilicon and arsenic. A deposition gas (e.g. silane) and a dopant gas (e.g. arsine) are thermally decomposed in the reaction chamber. During the deposition process the gas flows are pulsed relative to one another in some manner. This pulsed gas flows form a multi-layer stack which includes alternating deposition layers and doping layers. The dopants in the doping layer are then diffused during a subsequent annealing step (or during subsequent processing) into the deposition layers to form a uniformly doped thin film.

Abstract: The invention provides a hollow mill cutting tool capable of forming a cylindrical pin on one face of a plate member by removing material from the plate member. The cutting tool comprises a generally cylindrical member terminating in a tip portion having a toroidal cross-section and having its axis aligned with the cylindrical member. The inside diameter of the protruding end of the tip portion is selected to be the desired diameter of the cylindrical pin. The tip portion includes a plurality of forward helical surfaces each terminating at a forward end in a cutting edge extending across the thickness of the toroidal cross-section. Each helical surface extends rearwardly along a cylindrical path from the cutting edge at an angle of about 8.degree.-11.degree. with a plane transverse of the axis of the cylindrical member. A back helical surface, which is inclined at an angle of at least 55.degree. to a plane parallel to the axis, is connected to each of the foward helical surfaces.