Abstract: A PFM-type voltage regulator circuit converts an unregulated input voltage into a regulated output voltage using a first transistor controlled by a pulse control circuit and a second transistor controlled by a linear regulator circuit. The linear regulator circuit controls the second transistor when the regulated output voltage falls to a predetermined minimum target voltage level, thereby maintaining the regulated output voltage at the minimum target voltage level. The pulse control circuit detects the current passing through the second transistor, and in response generates a pulse signal having a predetermined duration that fully turns on the first transistor. The voltage through the first transistor is converted to an increasing inductor current that refreshes the regulated output voltage to a maximum target voltage level. When the pulse signal ends, the regulated output voltage again begins to fall toward the predetermined minimum target voltage level, and the cycle is repeated.

Abstract: A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.

Abstract: The present invention provides an apparatus and method for improving the accuracy of circuits. The apparatus includes a replicate circuit and a trim determination circuit. The trim determination circuit includes a measurable circuit element and determines the state of the measurable element. The replicate circuit includes a replicate circuit element which has similar electrical characteristics as the measurable element, and is configured to aid in determining an adjustable test current. The trim determination circuit generates a test current which is proportional to the adjustable test current. The test current is passed through the measurable element such that a first voltage drop occurs across the measurable element. A measured current is generated at a current level dictated by the voltage drop across the measurable element, such that the state of the measurable element is determined by the difference between the measured current and a scaled reference current.

Abstract: The present invention provides an apparatus and method for improving the accuracy of circuits. The apparatus includes a replicate circuit and a trim determination circuit. The trim determination circuit includes a measurable circuit element and determines the state of the measurable element. The replicate circuit includes a replicate circuit element which has similar electrical characteristics as the measurable element, and is configured to aid in determining an adjustable test current. The trim determination circuit generates a test current which is proportional to the adjustable test current. The test current is passed through the measurable element such that a first voltage drop occurs across the measurable element. A measured current is generated at a current level dictated by the voltage drop across the measurable element, such that the state of the measurable element is determined by the difference between the measured current and a scaled reference current.

Abstract: A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.

Abstract: The present invention provides an apparatus and method for improving the accuracy of circuits. The apparatus includes a replicate circuit and a trim determination circuit. The trim determination circuit includes a measurable circuit element and determines the state of the measurable element. The replicate circuit includes a replicate circuit element which has similar electrical characteristics as the measurable element, and is configured to aid in determining an adjustable test current. The trim determination circuit generates a test current which is proportional to the adjustable test current. The test current is passed through the measurable element such that a first voltage drop occurs across the measurable element. A measured current is generated at a current level dictated by the voltage drop across the measurable element, such that the state of the measurable element is determined by the difference between the measured current and a scaled reference current.

Abstract: An audio amplifier that does not exhibit a "pop" during a change-of-state such as being turned on. The popless amplifier includes an operational amplifier to power a speaker, a circuit to prevent the application of an output voltage from the operational amplifier to the speaker for a selectable period of time and a circuit to charge the output of the operational amplifier to a selectable mid-rail voltage during the time a voltage from the operational amplifier is prevented from reaching the speaker.

Abstract: A switching voltage regulator whose switching frequency decreases with reduced load currents is disclosed. The switching voltage regulator includes a current-controlled oscillator that varies the frequency of switching by changing the off-time of the switch and maintaining a constant on-time. The lower frequency as a result of the constant on-time switching reduces switching loss and power consumption at lower load currents. The constant on-time architecture of the present invention significantly improves the overall efficiency of the switching voltage regulator, while reducing component count and die size.

Abstract: A circuit for increasing the slew rate of linear amplifier circuits. The circuit comprises two NPN and PNP transistor pairs arranged so that when the voltage level difference between the amplifier output and input voltage exceeds the base to emitter voltage of such transistors, the circuit is activated. The circuit provides a current proportional to such voltage difference in order to speed up the charging or discharging of the slew rate determining capacitance.

Abstract: A track and hold circuit for producing an output voltage having a level related to the voltage level of an input voltage fed to the circuit during a track mode and for maintaining the level of the output voltage constant during a hold mode. The circuit includes a current source and a capacitor with the capacitor being charged with the current or discharged selectively in accordance with the level of the input voltage relative to the level of the output voltage to produce at the capacitor the voltage related to the voltage level of the input voltage. Current from the current source is directed away from the capacitor during the hold mode in order to reduce the effect of charge stored during the track mode from slowing the transition from track mode to hold mode operation.

Abstract: A precision amplifier that, in response to digital inputs, zeros its offset voltage. The precision amplifier comprises a traditional amplifier; a current source controlled by a counter; a comparator; test switches; and control logic. A digital input, such as might be generated from a microprocessor, initiates the offset adjustment. The test switches disconnect the amplifier inputs from external package connections and connect the inputs together. The counter begins to count, changing the current produced by the current source at each count. The current from the current source is applied to the offset adjust circuit of the amplifier which changes the offset voltage as the current changes. The counter counts until the comparator indicates the offset voltage has been zeroed. Alternative embodiments allow the precision amplifier to adjust for offset introduced by circuitry connected to the input and the output of the precision amplifier.

Abstract: An improved differential amplifier having circuitry to enhance the slew rate and to provide a means for nulling the offset voltage during fabrication of the amplifier as an integrated circuit. The differential amplifier comprises an input stage connected to a current mirror. A slew rate enhancement circuit injects current into selected points of the circuit when the input voltage exceeds a predetermined threshold. An offset trim circuit injects a selected amount of current into the current mirror to alter the current flow between the input stage and the current mirror, thereby reducing the offset voltage. The selected amount of current is dictated by diodes which may be permanently shorted at various stages during fabrication, both before and after the amplifier is enclosed in an IC package.

Abstract: An improved differential amplifier having circuitry to enhance the slew rate and to provide a means for nulling the offset voltage during fabrication of the amplifier as an integrated circuit. The differential amplifier comprises an input stage connected to a current mirror. A slew rate enhancement circuit injects current into selected points of the circuit when the input voltage exceeds a predetermined threshold. An offset trim circuit injects a selected amount of current into the current mirror to alter the current flow between the input stage and the current mirror, thereby reducing the offset voltage. The selected amount of current is dictated by diodes which may be permanently shorted at various stages during fabrication, both before and after the amplifier is enclosed in an IC package.

Abstract: An integrated circuit disposed in a package having a plurality of electrical interconnection leads, a first interconnection lead being adapted to receive an input signal during a normal operating mode of the integrated circuit. The integrated circuit comprises a supply voltage bus coupled to a second interconnection lead and fed by a reference potential and a differential amplifier comprising a pair of emitter-coupled transistors. The differential amplifier has a nominal offset voltage which is a function of a nominal resistance coupled between the collector electrode of a first one of the pair of emitter-coupled transistors and the reference potential. The nominal resistance is provided by a plurality of serially-coupled resistors.

Abstract: A digital-to-analog conversion circuitry is provided wherein a switching network is adapted to couple, or decouple, a selected one, or ones, of a plurality of identical current sources to, or from, an output bus selectively in accordance with the digital word being converted to produce an output current through an output bus having a level related to such digital word.

Abstract: A subsurface Zener diode is provided wherein a semiconductor has formed thereon spaced apart anode and cathode regions of opposite type conductivity, such regions having opposing surface portions, and disposed beneath a surface of such semiconductor a buried region of conductivity type the same as one of such regions, such buried region extending laterally through the spaced apart regions, one of the spaced apart regions having an opposing surface portion thereof formed with a portion which protrudes towards the opposing surface portion of the other one of the spaced apart regions. With such arrangement, an electric field produced between the spaced apart regions becomes concentrated at the protrusion with the result that Zener breakdown occurs repeatedly at the same point in the semiconductor thereby reducing long term drift. Also, a Kelvin buried Zener diode is provided by forming a second laterally spaced anode region with the cathode region disposed between the pair of anode regions.

Abstract: A switchable current source circuit having a current mirror and a switch, such switch including a current source coupled to the current mirror, such switch enabling or disabling current from the current source to pass to the input of the current mirror selectively in accordance with a control signal fed to such switch. In one embodiment, the switch includes a differential amplifier and the current source is part of the differential amplifier. One of a plurality of control signals is fed to control the differential amplifier with the differential amplifier serving as both a logic circuit and current source, therefore, reducing the number of circuit comparators required to provide a switchable current source circuit.

Abstract: A digital-to-analog conversion circuitry is provided wherein a switching network is adapted to couple, or decouple, a selected one, or ones, of a plurality of identical current sources to, or from, an output bus selectively in accordance with the digital word being converted to produce an output current through an output bus having a level related to such digital word.

Abstract: A differential amplifier is provided having a pair of input transistors with first electrodes connected to a first voltage potential through a first current source, a second pair of electrodes providing a pair of input terminals for the differential amplifier, and a third pair of electrodes connected to a pair of terminals, the current produced by the first current source passing through the first and third electrodes of the pair of input transistors into the pair of terminals in a ratio related to the difference in voltage of input signals fed to the pair of input terminals and the degree of mismatch in the pair of input transistors. A selector network injects a compensation current substantially equal to the difference in the currents passing through the pair of input transistors when the voltages at the pair of inputs are equal, and which results from a mismatch in such pair of input transistors, into a selected one of the pair of terminals.