Abstract: A system and a method for imaging a scene of interest utilize variable exposure periods that have durations based upon detecting a fixed voltage drop in order to determine the scene segment radiance. The rate of voltage drop corresponds to the degree of scene segment radiance, such that high radiant scene segments yield faster voltage drops than lower radiant scene segments. The variable exposure period is determined within each pixel in a pixel array of the system to gather exposure periods from different segments of the scene being imaged. The measured exposure periods are translated into grayscale information that can be used to generate a composite image having various levels of grayscale that is representative of the imaged scene. Each pixel includes a photo sensor, an analog-to-digital converter and a memory to measure, digitize and store the exposure period. The memory contains a number of memory cells having a three-transistor configuration that are each connected to a bi-directional bit line.

Abstract: An image sensor array. The image sensor array includes a substrate. An array of photo diode sensors are electrically interconnected to the substrate. The photo diode sensors conduct charge at a rate proportional to the intensity of light received by the photo diode sensors. A ring of guard diodes are located around the periphery of the array of photo diode sensors. Each guard diode has a guard diode anode connected to a predetermined guard anode voltage and a guard diode cathode connected to a static guard cathode voltage.

Abstract: An imaging device includes a Gray Code generator and an array of pixels. Each pixel includes a complimentary metal oxide semiconductor (“CMOS”) sensor, a comparator and random access memory (e.g., ferroelectric random access memory). The Gray Code generator is started at the beginning of capture mode and begins providing a sequence of code words. Within each pixel, an output of a CMOS sensor is compared to a threshold, and a code word in the sequence is stored in random access memory when the sensor output crosses the threshold. Thus, the random access memory of each pixel stores a code word that represents the intensity of light detected by its associated CMOS sensor.

Abstract: An imaging device includes a Gray Code generator and an array of pixels. Each pixel includes a complimentary metal oxide semiconductor (“CMOS”) sensor, a comparator and random access memory (e.g., ferroelectric random access memory). The Gray Code generator is started at the beginning of capture mode and begins providing a sequence of code words. Within each pixel, an output of a CMOS sensor is compared to a threshold, and a code word in the sequence is stored in random access memory when the sensor output crosses the threshold. Thus, the random access memory of each pixel stores a code word that represents the intensity of light detected by its associated CMOS sensor.

Abstract: A ferroelectric random access memory ("FeRAM") device includes shared bit lines and fragmented plate lines. Each bit line is shared by a group of two or more ferroelectric capacitors. Each group also includes at least one access transistor, which may be shared by more than one ferroelectric capacitor. During read and write operations, capacitors in a group are selected by the plate lines and a plate line decoder.

Abstract: A ferroelectric random access memory device ("FeRAM") includes an array of memory cells and a plurality of active read/write circuits for reading the memory cells. A memory cell is read by forcing its ferroelectric capacitor to a first polarization state and determining whether capacitor discharge exceeds a threshold. If the capacitor transitions from a second polarization state to the first polarization state, the capacitor discharge will exceed the threshold. If the threshold is exceeded, a logic value corresponding to the second polarization state is indicated, and the ferroelectric capacitor is restored to the second polarization state. If the ferroelectric capacitor does not transition from the first polarization state to the second polarization state (i.e., the capacitor remains in the first polarization state), capacitor discharge will not exceed the threshold. If the threshold is not exceeded, a logic value corresponding to the first polarization state is indicated.

Abstract: A field programmable gate array (FPGA) system for time multiplexing a plurality of programmable configurations of the FPGA. The system includes a plurality of configuration memory cells which are loaded with configuration information. A time slice selector couples selected configuration memory cells to programmable switch elements that determine the configuration and function of the logic within the FPGA. A time slice controller determines which of the configuration memory cells the time slice selector couples to the programmable switch elements. The configuration memory cells may be implemented with half SRAM cells and the time slice selector may be implemented with P-channel transistors.

Abstract: A field programmable gate array (FPGA) memory system which allows the same array of memory to contain both configurable memory and user memory. The FPGA user logic can modify the information contained within the configurable memory and the user memory. The information stored within the configuration memory defines the logic within the user logic. Therefore, the user logic can modify sections of the logic within the user logic. The configuration memory and the user memory share resources such as address decoders, bitlines and sense amplifiers.

Abstract: An on-chip voltage conversion circuit arrangement including charge pump logic circuitry, a dual-phase clock pulse circuit, and a comparator circuit. The dual-phase clock pulse circuit produces charge and pump pulses to drive the charge pump logic circuit while it is supplied with an input voltage level for conversion to a desired output voltage level. The charge pump logic circuit includes an output capacitor for producing the desired voltage level in a semiconductor chip to be fabricated. The output capacitor is supplied with electric charge during alternating charge and pump cycles from one or two charging capacitors. The output voltage is compared with a voltage reference permit enablement and disablement of charging and discharging action by the capacitors.

Abstract: An on-chip voltage conversion circuit arrangement including charge pump logic circuitry, a dual-phase clock pulse circuit, and a comparator circuit. The dual-phase clock pulse circuit produces charge and pump pulses to drive the charge pump logic circuit while it is supplied with an input voltage level for conversion to a desired output voltage level. The charge pump logic circuit includes an output capacitor for producing the desired voltage level in a semiconductor chip to be fabricated. The output capacitor is supplied with electric charge during alternating charge and pump cycles from one or two charging capacitors. The output voltage is compared with a voltage reference permit enablement and disablement of charging and discharging action by the capacitors.

Abstract: A semiconductor memory device is provided with a plurality of primary memory cell blocks and a replacement memory cell block identical in size to the primary memory cell blocks. The replacement memory block includes all the required analog row and column driver and sense circuitry for the memory cells contained in the replacement block. Each of the primary memory blocks has a laser fuse that will disable the associated primary memory block and enable the replacement memory block such that the total amount of logical memory in the memory device is unaffected by a defective primary block.

Abstract: An apparatus which corrects single bit errors and detects double bit errors including an encoder/decoder. During encoding the encoder/decoder produces a plurality of parity bits. These parity bits allow the correction of single bit errors in transmission. The encoder/decoder includes a plurality of arrays. Each array consists of logic gates arranged in the form of a binary tree. When the encoder/decoder is used in decoding, the encoder/decoder produces a plurality of syndrome bits. These syndrome bits are used to correct single bit errors in transmission. Error correction circuitry composed of logic gates receive the syndrome bits and generate flipper bits used in error correction. When a first data bit for which a first flipper bit is being generated is used in the production of a majority of syndrome bits, a logic gate which generates the first flipper bit receives as input only syndrome bits in the production of which the first data bit was used.