Abstract: A SONET interface line unit which includes an interface to a SONET ring, an STM switch fabric, and STM synchronization function within a single module. The line unit includes an optical interface for communicating SONET traffic with a SONET ring, an ATM interface for communicating ATM traffic with an ATM switch fabric unit, and two or more service unit interfaces for communicating with service units having service interfaces to a service side of a network element. The service unit interfaces operate using the STM protocol. The line unit further includes forwarding logic for extracting ATM traffic and STM traffic from the composite traffic received from the SONET ring. The line unit further provides synchronization signals to other units within the network element, derived from a selected timing reference signal. An extended synchronization module is used to interface to a larger number of timing references within the device.

Abstract: A circuit for recovering a clock signal from incoming data and for retiming the incoming data comprises circuitry for generating a plurality of phased clock signals responsive to a selected frequency and clock recovery circuitry for generating a recovered clock from the plurality of phased clocks and the incoming data. The recovered clock is used to retime the data, which may be either RZ or NRZ data. To recover clock from the incoming data, the presence of a logic "1" is detected in one or more data streams and the phase of the data relative to the phased clocks is determined. Hold circuitry stores the phase information during the interval between logic "1" bits and aligns the phase information with the leading phased clock. Compare circuitry and counter circuitry detect changes in phase information to insure that a change is not merely the result of a metastable anomaly.

Abstract: A circuit for recovering a clock signal from incoming data and for retiming the incoming data comprises circuitry for generating a plurality of phased clock signals responsive to a selected frequency and clock recovery circuitry for generating a recovered clock from the plurality of phased clocks and the incoming data. The recovered clock is used to retime the data, which may be either RZ or NRZ data. To recover clock from the incoming data, the presence of a logic "1" is detected in one or more data streams and the phase of the data relative to the phased clocks is determined. Hold circuitry stores the phase information during the interval between logic "1" bits and aligns the phase information with the leading phased clock. Compare circuitry and counter circuitry detect changes in phase information to insure that a change is not merely the result of a metastable anomaly.

Abstract: A circuit for using a high speed clock and a counter to obtain a recovered clock with incoming data resetting the counter whenever a logic "1" of more than a predetermined number of high speed clocks is received. Further, the presence of a data out logic "1" inhibits the reaction of the circuit to any further input pulses during the time necessary to generate the retimed data output logic "1".