Abstract: A routing bits generator is associated with one or more reverse Omega networks with L stages and 2.sup.N inputs. 2.sup.N state bits, indicating whether the cells to be routed are free or occupied, are loaded in parallel into a state register, then shifted in series in this register. The state bits delivered successively by the serial output of the state register, filtered if L<N, serve to increment a first counter or decrement a second counter depending on the values of the state bits, and to select one or the other of the two counters at the input of a multiplexer. L addressing registers, receiving in serial shift mode the L address bits provided by the multiplexer, are cascaded in such a way that after 2.sup.N serial shift cycles, their contents can be transferred in parallel to means inserting the address bits at the head of the cells.