Patents by Inventor Charles Moana Hook
Charles Moana Hook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9218895Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).Type: GrantFiled: August 5, 2014Date of Patent: December 22, 2015Assignee: SanDisk Technologies Inc.Inventors: Charles Moana Hook, Loc Tu, Nyi Nyi Thein, James Floyd Cardosa, Ian Arthur Myers
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Publication number: 20140351653Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).Type: ApplicationFiled: August 5, 2014Publication date: November 27, 2014Inventors: Charles Moana Hook, Loc Tu, Nyi Nyi Thein, James Floyd Cardosa, Ian Arthur Myers
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Patent number: 8826086Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).Type: GrantFiled: February 7, 2011Date of Patent: September 2, 2014Assignee: SanDisk Technologies Inc.Inventors: Charles Moana Hook, Loc Tu, Nyi Nyi Thein, James Floyd Cardosa, Ian Arthur Myers
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Patent number: 8446772Abstract: Techniques are disclosed herein for automatically self-disabling a memory die in the event that a programmable element on the memory die for indicating whether the memory die is defective cannot be trusted. Memory die are provided with chip enable circuitry to allow particular memory die to be disabled. If the programmable element can be trusted, the state of the programmable element is provided to the chip enable circuitry to enable/disable the memory die based on the state. However, if the programmable element cannot be trusted, then the chip enable circuitry may automatically disable the memory die. This provides a greater yield for multi-chip memory packages because packages having memory die with a programmable element that cannot be trusted can still be used.Type: GrantFiled: August 4, 2011Date of Patent: May 21, 2013Assignee: SanDisk Technologies Inc.Inventors: Loc Tu, Charles Moana Hook, Nyi Nyi Thein
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Publication number: 20130033935Abstract: Techniques are disclosed herein for automatically self-disabling a memory die in the event that a programmable element on the memory die for indicating whether the memory die is defective cannot be trusted. Memory die are provided with chip enable circuitry to allow particular memory die to be disabled. If the programmable element can be trusted, the state of the programmable element is provided to the chip enable circuitry to enable/disable the memory die based on the state. However, if the programmable element cannot be trusted, then the chip enable circuitry may automatically disable the memory die. This provides a greater yield for multi-chip memory packages because packages having memory die with a programmable element that cannot be trusted can still be used.Type: ApplicationFiled: August 4, 2011Publication date: February 7, 2013Inventors: Loc Tu, Charles Moana Hook, Nyi Nyi Thein
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Publication number: 20120201091Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).Type: ApplicationFiled: February 7, 2011Publication date: August 9, 2012Inventors: Charles Moana Hook, Loc Tu, Nyi Nyi Thein, James Floyd Cardosa, Ian Arthur Myers
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Patent number: 8018769Abstract: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be used to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.Type: GrantFiled: October 5, 2009Date of Patent: September 13, 2011Assignee: Sandisk Technologies Inc.Inventors: Loc Tu, Charles Moana Hook, Yan Li
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Publication number: 20100020614Abstract: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be used to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.Type: ApplicationFiled: October 5, 2009Publication date: January 28, 2010Inventors: LOC TU, CHARLES MOANA HOOK, YAN LI
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Patent number: 7606077Abstract: High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.Type: GrantFiled: September 12, 2006Date of Patent: October 20, 2009Assignee: SanDisk CorporationInventors: Yan Li, Loc Tu, Charles Moana Hook
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Patent number: 7606091Abstract: High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.Type: GrantFiled: September 12, 2006Date of Patent: October 20, 2009Assignee: SanDisk CorporationInventors: Yan Li, Loc Tu, Charles Moana Hook
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Patent number: 7599223Abstract: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.Type: GrantFiled: September 12, 2006Date of Patent: October 6, 2009Assignee: SanDisk CorporationInventors: Loc Tu, Charles Moana Hook, Yan Li
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Patent number: 7453731Abstract: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.Type: GrantFiled: September 12, 2006Date of Patent: November 18, 2008Assignee: Sandisk CorporationInventors: Loc Tu, Charles Moana Hook, Yan Li
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Publication number: 20080062785Abstract: High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.Type: ApplicationFiled: September 12, 2006Publication date: March 13, 2008Inventors: Yan Li, Loc Tu, Charles Moana Hook
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Publication number: 20080062765Abstract: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.Type: ApplicationFiled: September 12, 2006Publication date: March 13, 2008Inventors: Loc Tu, Charles Moana Hook, Yan Li
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Publication number: 20080062770Abstract: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.Type: ApplicationFiled: September 12, 2006Publication date: March 13, 2008Inventors: Loc Tu, Charles Moana Hook, Yan Li
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Publication number: 20080062768Abstract: High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.Type: ApplicationFiled: September 12, 2006Publication date: March 13, 2008Inventors: Yan Li, Loc Tu, Charles Moana Hook