Abstract: An imaging pixel array and associated method and system are disclosed in which the array contains first pixels each having a first photo-conversion device, and second pixels each having a first photo-conversion device and a second photo-conversion device. The first photo-conversion devices are configured to acquire an image during a first integration period. The second photo-conversion devices are configured to acquire a plurality of images during the first integration period. A circuit uses the plurality of image signals and determines from them relative motion between the array and an image during a portion of the first integration period and provides a signal representing the motion which is used for image stabilization.

Abstract: A sound suppressor suppresses sound and flash by creating interacting paths of gas. While a first portion of the gas follows a first path through the suppressor, a second portion of the gas is diverted radially from the first path to a second path and then repeatedly made to cross the first path by a series of baffles with alternating radial passages so that the two portions of gas interfere and interact with each other, and therefore quickly give up much of their kinetic energy before they exit the suppressor. Preferably, the baffles defining the second path impart a swirl to the second portion of gas to cause the present suppressor to flush itself of carbon and metal particles. The interaction of the two portions also accelerates completion of combustion of the gas to thereby reduce flash.

Abstract: The present invention relates to the provision of a polynucleotide comprising one or more functional fragments of a biosynthetic gene cluster involved in the production of a compound of formula (I) or (I?). The present invention also provides a method of preparing a compound of formula (I) or (I?) or of formula (II) to (VII), (XI) to (XIV) and (XVII) and (XVIII). Moreover, the use of such compound as a pharmaceutical composition is also provided in the present invention.

Abstract: The invention relates generally to novel macrolactams and their analogs, to processes for the preparation of these novel macrolactams, to pharmaceutical compositions comprising the novel macrolactams; and to methods of using the novel macrolactams to treat or inhibit various disorders.

Abstract: An inspection head where non-destructive inspection is structured to fit into narrow spaces, and to accurately and repeatably move an inspection probe along a surface to be inspected. Movement of the inspection head along an X, Y, Z, ?, and ?-axis is precisely controlled by individual drive mechanisms.

Abstract: An enhanced visibility system for utility vehicles is disclosed. The visibility system may enhance an operator's view from the utility vehicle by making an obstruction appear transparent to the operator.

Abstract: A method and apparatus for determining the burst bit rate for data in the transport layer of a network is described. The burst bit rate is determined by measuring the time for a total number of bytes to be transferred across a point in the network and adding that time to an estimated network delay. The total number of bytes transferred is then divided by the transfer time plus the estimated network delay thereby calculating the burst bit rate for the transfer.

Abstract: An architecture for error log processing is provided. Each error log is given a defined priority and mapped to an error recovery procedure (ERP) to be run if the log is seen. The system has a plurality of software layers to process the errors. Each software layer processes the error independently. Errors are reported to a higher software stack when error recovery fails from the lower stack ERPs and recovery is non-transparent. If the system host identified for error processing fails, the control of the ERP is transferred during the failover process. Non-obvious failed component isolating ERPs are grouped to be run together to assist in isolating the failed component. Prioritization of the error systems may be based on a plurality of criteria. ERPs are assigned to run within a particular software stack.

Abstract: The present invention relates to a central vacuum cleaning system for vehicles. The unit comprises a vacuum generating alternating current motor, a built-in direct current to alternating current inverter and a removable dirt cup containing a filter and screen. The unit has a built-in in-take port, which has an auto switch that turns the unit on when the vacuum hose is plugged in and shuts the unit off when the vacuum hose is unplugged. The unit also has a remote in-take and remote auto switch capability so you can plug the vacuum hose into a more convenient location in the interior of the vehicle. The unit can be mounted horizontally or vertically. The unit can be installed in any vehicle consisting of a 12-volt direct current battery. The vehicle does not need to have an alternating current inverter installed separately to operate.

Abstract: A vehicle is disclosed having a blade control system. The blade control system is provided to adjust the angle of a blade and to adjust the pitch of the blade. A method for adjusting the pitch of the blade is also disclosed.

Abstract: The invention relates generally to novel macrolactams and their analogs, to processes for the preparation of these novel macrolactams, to pharmaceutical compositions comprising the novel macrolactams; and to methods of using the novel macrolactams to treat or inhibit various disorders.

Abstract: An imaging pixel array and associated method and system are disclosed in which the array contains first pixels each having a first photo-conversion device, and second pixels each having a first photo-conversion device and a second photo-conversion device. The first photo-conversion devices are configured to acquire an image during a first integration period. The second photo-conversion devices are configured to acquire a plurality of images during the first integration period. A circuit uses the plurality of image signals and determines from them relative motion between the array and an image during a portion of the first integration period and provides a signal representing the motion which is used for image stabilization.

Abstract: The invention relates generally to novel macrocyclic polyene lactams and their analogs, to processes for the preparation of these novel macrocyclic polyene lactams, to pharmaceutical compositions comprising the novel macrocyclic polyene lactams; and to methods of using the novel macrocyclic polyene lactams to treat or inhibit various disorders.

Abstract: A system and method for measuring user-perceived delay in an IP network, comprising detecting request and corresponding response messages at a monitoring point in the network, calculating an uplink delay based upon the time elapsed between the request and corresponding response messages, detecting response and corresponding transport acknowledgement messages at the monitoring point, wherein the response message is sent in response to the request message, calculating a downlink network delay based upon the time elapsed between the response and corresponding transport acknowledgement messages; and calculating a user-perceived delay by adding uplink delay and downlink network delay, wherein the user-perceived delay represents a time required for an IP message to travel from a user device to a network destination plus the time required for the service (server) to respond and return the response to the user device.

Abstract: An inspection head where non-destructive inspection is structured to fit into narrow spaces, and to accurately and repeatably move an inspection probe along a surface to be inspected. Movement of the inspection head along an X, Y, Z, ?, and ?-axis is precisely controlled by individual drive mechanisms.

Abstract: An architecture for error log processing is provided. Each error log is given a defined priority and mapped to an error recovery procedure (ERP) to be run if the log is seen. The system has a plurality of software layers to process the errors. Each software layer processes the error independently. Errors are reported to a higher software stack when error recovery fails from the lower stack ERPs and recovery is non-transparent. If the system host identified for error processing fails, the control of the ERP is transferred during the failover process. Non-obvious failed component isolating ERPs are grouped to be run together to assist in isolating the failed component. Prioritization of the error systems may be based on a plurality of criteria. ERPs are assigned to run within a particular software stack.

Abstract: A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status.

Abstract: A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status.

Abstract: A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status.

Abstract: A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status.