Abstract: Innovations in content mastering operations performed during playback of high dynamic range (“HDR”) video on a display device are described. When content mastering is performed during playback on a display device, a video playback system can use details retained for input HDR video (e.g., retained in metadata) and the properties of the display device to improve the perceptual quality of the HDR video as shown on that display device. For example, the video playback system can use an energy-preserving bloom operator to make bright highlights “bloom” into adjacent areas, thereby accentuating the bright highlights in the HDR video while operating within the constraints of the display device. The video playback system can also perform various other types of operations when content mastering is deferred until playback, including application of a lens flare operator as well as alternative tone mapping operators and alternative color gamut mapping operators selected according to metadata.

Abstract: Innovations in content mastering operations performed during playback of high dynamic range (“HDR”) video on a display device are described. When content mastering is performed during playback on a display device, a video playback system can use details retained for input HDR video (e.g., retained in metadata) and the properties of the display device to improve the perceptual quality of the HDR video as shown on that display device. For example, the video playback system can use an energy-preserving bloom operator to make bright highlights “bloom” into adjacent areas, thereby accentuating the bright highlights in the HDR video while operating within the constraints of the display device. The video playback system can also perform various other types of operations when content mastering is deferred until playback, including application of a lens flare operator as well as alternative tone mapping operators and alternative color gamut mapping operators selected according to metadata.

Abstract: Methods, systems, and devices are described herein for encoding, decoding, and otherwise processing in hardware and/or software a high dynamic range (HDR) color data structure. In one example, a method for encoding pixel data may include receiving pixel data comprising a red, green, and blue (RGB) value. The method may further include transforming the received pixel data to an intermediate color space data, such as transformed CIE AYB space data. The method may further include compressing the intermediate color space data into less than 64 bits, such as 32 bits. In some aspects, the 32 bits may be divided into luminance information and chrominance information, including, for example, 14 bits representing a floating point luminance value, and 9 bits each representing two fixed point chrominance channel values.

Abstract: Methods, systems, and computer-storage media for target independent rasterization of an image. The target is the memory allocated for a rendered image within a graphics pipeline. Embodiments of the present invention allow the rasterization process's sampling rate to be specified independently from the memory allocated for the rendered image. Embodiments of the present invention also allow the rasterization process to be executed at a rate that does not correspond to the memory allocated for the rendered target.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: Systems and associated methods for processing textures in a graphical processing unit (GPU) are disclosed. Textures may be managed on a per region (e.g., tile) basis, which allows efficient use of texture memory. Moreover, very large textures may be used. Techniques provide for both texture streaming, as well as sparse textures. A GPU texture unit may be used to intelligently clamp LOD based on a shader specified value. The texture unit may provide feedback to the shader to allow the shader to react conditionally based on whether clamping was used, etc. Per region (e.g., per-tile) independent mipmap stacks may be used to allow very large textures.

Abstract: Systems and methods for utilizing intermediate target(s) in connection with computer graphics in a computer system allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: Utilizing intermediate target(s) in connection with computer graphics in a computer system is provided. In various embodiments, intermediate memory buffers in video memory are provided and utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips.

Abstract: Methods, systems, and computer-storage media for target independent rasterization of an image. The target is the memory allocated for a rendered image within a graphics pipeline. Embodiments of the present invention allow the rasterization process's sampling rate to be specified independently from the memory allocated for the rendered image. Embodiments of the present invention also allow the rasterization process to be executed at a rate that does not correspond to the memory allocated for the rendered target.

Abstract: Systems and associated methods for processing textures in a graphical processing unit (GPU) are disclosed. Textures may be managed on a per region (e.g., tile) basis, which allows efficient use of texture memory. Moreover, very large textures may be used. Techniques provide for both texture streaming, as well as sparse textures. A GPU texture unit may be used to intelligently clamp LOD based on a shader specified value. The texture unit may provide feedback to the shader to allow the shader to react conditionally based on whether clamping was used, etc. Per region (e.g., per-tile) independent mipmap stacks may be used to allow very large textures.

Abstract: Intermediate target(s) are utilized in connection with computer graphics in a computer system. In various embodiments, intermediate memory buffers in video memory are utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.

Abstract: An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.