Abstract: A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit utilizing the host site and the customer site connected though a wide area network (wherein the host site contains the core logic and the customer site contains customer logic, the core logic and the customer logic forming the circuit), comparing test output signals with the desired output signals, and altering the customer logic until the test output signals are consistent with the desired output signals.

Abstract: A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.

Abstract: A system and method for interconnecting a plurality of cores into a single functional core. The method involves creating for each core a pin configuration structure based on a set of configuration rules. When the cores to be interconnected are selected, the pin configuration structure is accessed by the configurator program tool of the present invention. The configurator program tool then connects the cores together using the pin configuration structure and configuration rules for the selected cores. The configurator program tool generates an error-free high level model of the interconnected cores. The configurator program tool allows configuration flexibility and is general enough to handle most configuration scenarios. The tool is also easy to code, extensible, and can be applied to existing core designs with no modification of the cores themselves.

Abstract: A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.

Abstract: A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.