Patents by Inventor Charles Narad

Charles Narad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8549256
    Abstract: Methods and apparatus relating to a tightly coupled scalar and Boolean processor are described. In an embodiment, a Boolean unit may include a result vector subunit. The result vector subunit may be controlled by an instruction flow that is managed by a scalar unit. Other embodiments are also disclosed.
    Type: Grant
    Filed: January 15, 2007
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventor: Charles Narad
  • Patent number: 7886102
    Abstract: Embodiments are generally directed to an apparatus for determining compatibility between devices. In one embodiment, a table including a module's parameters and rules associated therewith is obtained from a module. The rules are applied to a slot's parameters to determine the module's compatibility with the slot upon coupling to the slot.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventor: Charles Narad
  • Patent number: 7761666
    Abstract: A method and apparatus for placement of temporary relevant data are disclosed. In one embodiment, the apparatus comprising one or more memories through which a producer provides data for access by a consumer in a memory-based producer-consumer relationship, and an agent to monitor access by the producer and consumer to the one or more memories and to direct placement of produced data into at least one of the one or more memories that is closer to the consumer, wherein placement occurs at a time determined by the agent.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: July 20, 2010
    Assignee: Intel Corporation
    Inventors: Charles Narad, Raj Yavatkar
  • Patent number: 7573879
    Abstract: Embodiments are generally direct to a method and apparatus for generating a header in a communication network. In one embodiment, receiving at a node on a first communication link a protocol data unit (PDU), generating a header that is non-specific to a particular communication protocol associated with the PDU when received at the node, the header to facilitate encapsulation and transportation of the PDU through a second communication link to deliver the PDU to a memory-based service interface of another node on the second communication link.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: August 11, 2009
    Assignee: Intel Corporation
    Inventors: Charles Narad, Joseph Bennett
  • Publication number: 20090070512
    Abstract: Embodiments are generally directed to an apparatus for determining compatibility between devices. In one embodiment, a table including a module's parameters and rules associated therewith is obtained from a module. The rules are applied to a slot's parameters to determine the module's compatibility with the slot upon coupling to the slot.
    Type: Application
    Filed: October 28, 2008
    Publication date: March 12, 2009
    Inventor: Charles Narad
  • Patent number: 7464212
    Abstract: Embodiments are generally directed to a method and apparatus for determining compatibility between devices. In one embodiment, a table including a module's parameters and rules associated therewith is obtained from a module. The rules are applied to a slot's parameters to determine the module's compatibility with the slot upon coupling to the slot.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: December 9, 2008
    Assignee: Intel Corporation
    Inventor: Charles Narad
  • Patent number: 7447233
    Abstract: A method and system to aggregate packets. A plurality of packets are received from a medium. The packets are aggregated into a single Advanced Switching (“AS”) packet and transmitted onto an AS fabric as a single AS packet.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: November 4, 2008
    Assignee: Intel Corporation
    Inventors: Charles Narad, Dave Gish
  • Publication number: 20080104325
    Abstract: A method and apparatus for placement of temporary relevant data are disclosed. In one embodiment, the apparatus comprising one or more memories through which a producer provides data for access by a consumer in a memory-based producer-consumer relationship, and an agent to monitor access by the producer and consumer to the one or more memories and to direct placement of produced data into at least one of the one or more memories that is closer to the consumer, wherein placement occurs at a time determined by the agent.
    Type: Application
    Filed: October 26, 2006
    Publication date: May 1, 2008
    Inventors: Charles Narad, Raj Yavatkar
  • Publication number: 20070169179
    Abstract: Methods and apparatus relating to a tightly coupled scalar and Boolean processor are described. In an embodiment, a Boolean unit may include a result vector subunit. The result vector subunit may be controlled by an instruction flow that is managed by a scalar unit. Other embodiments are also disclosed.
    Type: Application
    Filed: January 15, 2007
    Publication date: July 19, 2007
    Applicant: INTEL CORPORATION
    Inventor: Charles Narad
  • Patent number: 7246205
    Abstract: Methods, software and systems of dynamically controlling push cache operations are presented. One method, which may also be implemented in software and/or hardware, monitors performance parameters and enables or disables push cache operations depending on whether the performance parameters are within a predetermined range. Another method, which may also be implemented in software and/or hardware, monitors an amount of credits associated with a device and enables or disables push cache operations dependent upon whether the device has sufficient remaining credits.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: July 17, 2007
    Assignee: Intel Corporation
    Inventors: Santosh Balakrishnan, Raj Yavatkar, Charles Narad
  • Publication number: 20070143546
    Abstract: Some of the embodiments discussed herein may utilize partitions within a shared cache in various computing environments. In an embodiment, data shared between two memory accessing agents may be stored in a shared partition of the shared cache. Additionally, data accessed by one of the memory accessing agents may be stored in one or more private partitions of the shared cache.
    Type: Application
    Filed: December 21, 2005
    Publication date: June 21, 2007
    Inventor: Charles Narad
  • Publication number: 20060236011
    Abstract: The disclosure describes techniques used by one or more producers and consumers of one or more rings.
    Type: Application
    Filed: April 15, 2005
    Publication date: October 19, 2006
    Inventors: Charles Narad, Mark Rosenbluth
  • Publication number: 20060136671
    Abstract: Methods, software and systems of dynamically controlling push cache operations are presented. One method, which may also be implemented in software and/or hardware, monitors performance parameters and enables or disables push cache operations depending on whether the performance parameters are within a predetermined range. Another method, which may also be implemented in software and/or hardware, monitors an amount of credits associated with a device and enables or disables push cache operations dependent upon whether the device has sufficient remaining credits.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 22, 2006
    Inventors: Santosh Balakrishnan, Raj Yavatkar, Charles Narad
  • Publication number: 20060123165
    Abstract: Embodiments are generally directed to a method and apparatus for determining compatibility between devices. In one embodiment, a table including a module's parameters and rules associated therewith is obtained from a module. The rules are applied to a slot's parameters to determine the module's compatibility with the slot upon coupling to the slot.
    Type: Application
    Filed: December 6, 2004
    Publication date: June 8, 2006
    Inventor: Charles Narad
  • Publication number: 20060072615
    Abstract: A method and system to aggregate packets. A plurality of packets are received from a medium. The packets are aggregated into a single Advanced Switching (“AS”) packet and transmitted onto an AS fabric as a single AS packet.
    Type: Application
    Filed: September 29, 2004
    Publication date: April 6, 2006
    Inventors: Charles Narad, Dave Gish
  • Publication number: 20060050739
    Abstract: Embodiments are generally direct to a method and apparatus for generating a header in a communication network. In one embodiment, receiving at a node on a first communication link a protocol data unit (PDU), generating a header that is non-specific to a particular communication protocol associated with the PDU when received at the node, the header to facilitate encapsulation and transportation of the PDU through a second communication link to deliver the PDU to a memory-based service interface of another node on the second communication link.
    Type: Application
    Filed: September 3, 2004
    Publication date: March 9, 2006
    Inventors: Charles Narad, Joseph Bennett
  • Publication number: 20050111448
    Abstract: In general, in one aspect, the disclosure describes a method of generating, at a first component, a packet having a header and payload that includes data originating within the first component. The method also includes transmitting the packet to a second component further along a receive path monotonically ascending layers of a protocol stack.
    Type: Application
    Filed: November 25, 2003
    Publication date: May 26, 2005
    Inventor: Charles Narad
  • Publication number: 20050114536
    Abstract: In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory accessed by at least one processor.
    Type: Application
    Filed: November 25, 2003
    Publication date: May 26, 2005
    Inventor: Charles Narad