Abstract: Systems and methods for synchronizing pulse width modification for a dual inverter system are disclosed. For example, a method for synchronizing pulse width modulation (PWM) of a master inverter and a slave inverter may include: receiving a PWM command at a master PWM generator of the master inverter from a master central processing unit (CPU) communicatively coupled to the master PWM generator; generating a synchronization pulse at the master inverter; determining at a slave CPU communicatively coupled to a slave PWM generator of the slave inverter a phase shift error from the synchronization pulse; and adjusting a phase of the slave inverter PWM using the determined phase shift error.

Abstract: Methods and systems are provided for modulating undesired electric-motor braking. Based upon the detection of an inverter degradation event, one of a first gate driver and a second gate driver (e.g., a high gate driver and a low gate driver, such as for one phase of an inverter) may be asserted in an alternating manner while the other of the first gate driver and a second gate driver is de-asserted, and the first gate driver and second gate driver may then be provided to a power switch circuitry. The alternating assertion of the one of the first gate driver and the second gate driver may be associated with a higher-speed state, and the de-assertion of both the first gate driver and the second gate driver may be associated with a lower-speed state.

Abstract: Methods and systems are provided for modulating undesired electric-motor braking. Based upon the detection of an inverter degradation event, one of a first gate driver and a second gate driver (e.g., a high gate driver and a low gate driver, such as for one phase of an inverter) may be asserted in an alternating manner while the other of the first gate driver and a second gate driver is de-asserted, and the first gate driver and second gate driver may then be provided to a power switch circuitry. The alternating assertion of the one of the first gate driver and the second gate driver may be associated with a higher-speed state, and the de-assertion of both the first gate driver and the second gate driver may be associated with a lower-speed state.

Abstract: A multiple-phase electric machine provided with multiple inverter power circuits is described herein. The present multiple-phase electric machine aim at performing configuration changes while reducing the loss of torque when machines are switched between configurations. This is done by forming groups of phases defining machine portions that are powered by a separate inverter power circuit and by switching the machine portions separately with controlled switching devices.

Abstract: A multiple-phase electric machine provided with multiple inverter power circuits is described herein. The present multiple-phase electric machine aim at performing configuration changes while reducing the loss of torque when machines are switched between configurations. This is done by forming groups of phases defining machine portions that are powered by a separate inverter power circuit and by switching the machine portions separately with controlled switching devices.