Abstract: A digital signal processor (DSP) for conducting arithmetically complex functions, is provided. The DSP is preferably embodied as a single integrated circuit chip and generally includes a microinstruction sequencer (MIS) section, an arithmetic logic unit (ALU), a serial arithmetic processor section, a RAM section, and a system data bus. The MIS includes a coded ROM, a circuit for addressing the ROM, a ROM decoder for decoding the ROM code into control and data signals, and circuitry for sending the control and data signals to desired locations, and controls the functioning of the DSP. The ALU performs arithmetic and logic functions under the control of the ROM, while the serial arithmetic processor section conducts arithmetically complex functions under the control of the ROM. The RAM, under control of the ROM receives and stores data which is sent to the RAM via a system data bus directly from the ROM, from the ALU, from the serial arithmetic processor, and from circuitry exterior to the DSP.

Abstract: A microinstruction sequencer capable of directing an arithmetic-logic unit to conduct conditional operations is disclosed and generally includes a ROM and a selection circuit. The ROM has a memory of m bits wide and n words long, wherein for an m bit wide word in the ROM which defines a conditional operation, a first plurality of bits of the m bits are allocated to a first set of bits for instructing the arithmetic-logic unit as to the function it is to perform, a second plurality of bits of the m bits are allocated to a second set of bits for instructing the arithmetic-logic unit as to the function it is to perform, and a third plurality of bits of the m bits are allocated to a set of control bits. The selecting circuit selects one set of bits from at least the first and second set of bits, and includes a controller for receiving the control bits and controlling the selection by the selection circuit in response thereto.

Abstract: A parallel arithmetic-logic unit (PALU) controlled by a microinstruction sequencer and capable of executing conditional operations in a single pass is disclosed. The PALU generally comprises first and second registers for storing data, a comparator for continually comparing the values in the registers, and an arithmetic-logic core connected to the registers for performing arithmetic, logical and data move operations on the data in the registers. The comparator is preferably an unsigned magnitude comparator which outputs flags indicative of the relative status of the values in the registers. The flags are read by a microinstruction sequencer which then uses the flag information to determine what operation the arithmetic-logic core is to conduct. Preferably, a shifter is also provided between one of the registers and the arithmetic-logic core.

Abstract: A serial arithmetic processor arranged to perform the complex arithmetic functions of the Adaptive Differential Pulse Coded Modulation (ADPCM) algorithm. The serial arithmetic processor includes a first common circuit which is arranged to take advantage of the realization that a large portion of the LOG, FLOAT, and ANTILOG functions can be implemented in common hardware. The serial arithmetic processor further includes a second common circuit which is arranged to take advantage of the realization that large portions of the MULTIPLICATION and FLOATING POINT MULTIPLICATION functions can be implemented in other common hardware. A controller is provided for controlling logic and other circuitry in the first and second common circuits depending upon the desired function to be performed.