Abstract: A process to form poly sidegate LDD structures on buried channel MOSFETs is described. A polysilicon spacer is formed on the gate after source/drain processing. The spacer is later shorted to the main gate by implantation of neutral impurities. The process is particularly suited for SOI technology.

Abstract: A process for making borderless contacts through an insulating layer to active regions of a semiconductor device is disclosed. After deposition of a silicon nitride layer and an insulation glass layer on a substrate coating semiconductor devices, the contact windows are etched. The windows are etched through the glass layer with BCl.sub.2 or CHF.sub.3 /CF.sub.4 etch gases. Next, the windows are etched through the silicon nitride with CH.sub.3 F or O.sub.2 /CHF.sub.3 gases.

Abstract: A method of planarizing wide dielectric filled isolation trenches formed in the surface of a semiconductor surface is described. A self aligned mask is formed on the thick conformal layer of dielectric in the depressions over the wide trenches to protect the dielectric in those trenches from etching during planarization steps. The mask material is chosen to have etch characteristics different from the dielectric layer and a subsequent planarizing organic layer to allow selective etching of the mask material or dielectric without etching the other materials in the structure.