Abstract: Disclosed is a memory system for storing digital data; the memory system of the type which may be implemented, for instance, in an electronic microprocessor or calculator system. The memory comprises an array of transistor memory cells arranged in columns and rows. Column conductors are provided for supplying digital information to each column of such cells and row conductors are provided for enabling each row of cells to store digital information being received on the column conductors. A commutator is provided for successively supplying enabling signals to the row conductors and another commutator is provided for successfully connecting the column conductors with an input/output bus in the memory system. The provision of the commutators with the array of memory cells causes the data, when stored as a word of data, to occupy a register arranged in essentially a diagonal pattern through the array.

Abstract: An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is provided with a semiconductor chip having a memory for storing instruction words, an arithmetic unit, an instruction word decoder for controlling the arithmetic unit in response to instruction commands read out of the instruction word memory and a combined data and flag bit storage system. The combined data and flag bit storage system provides for the storage of flag bits with an associated numeric data word in a single register. Certain of the stages of the register are preferably dedicated for use as flag bit storage and certain other stages of the register are dedicated for use as numeric data storage. The arithmetic unit is preferably operable in a first mode for performing arithmetic operations in binary coded decimal format for the numeric data and in a binary format for the flag bits.

Abstract: An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is provided with a semiconductor chip having an arithmetic unit, a memory register and a dual speed shift register, the dual speed shift register being responsive to control signals generated on the chip for controlling the memory register to selectively read out a first or second number of digits of data stored therein to an input of the arithmetic unit.

Abstract: A calculator system, implemented on at least one semiconductor chip and having a read-only-memory for storing a plurality of program instructions, has a multi-function memory instruction register. The instruction register has a parallel input for receiving a selected program instruction from the memory, and preferably a parallel output for transmitting the program instruction to a decoder. The instruction register also has a serial output connected to a buffer. The memory is addressed by an address register which also provides a code indicative of whether or not the addressed program instruction is to control the calculator system. When the addressed program instruction is to control the system, the code has preselected setting and the program instruction is read out of the instruction register through the buffer and is sequentially serially re-entered into the instruction register via a serial input. Thereafter, the program instruction is read out of the instruction register to be decoded by the decoder.

Abstract: Disclosed is a calculator having a basic pair of semiconductor chips respectively providing memory and computational functions and a third chip in combination therewith providing additional register and memory capacity. The basic chip pair generates system timing signals, flag signals and control signals which address the registers on the third chip and allow data to be written there into via the input/output data lines and data to be read therefrom via the input/output lines. The specific functions are effected upon the occurrence of the flag signal concurrently with a preselected timing signal.