Abstract: Disclosed is a memory system for storing digital data; the memory system of the type which may be implemented, for instance, in an electronic microprocessor or calculator system. The memory comprises an array of transistor memory cells arranged in columns and rows. Column conductors are provided for supplying digital information to each column of such cells and row conductors are provided for enabling each row of cells to store digital information being received on the column conductors. A commutator is provided for successively supplying enabling signals to the row conductors and another commutator is provided for successfully connecting the column conductors with an input/output bus in the memory system. The provision of the commutators with the array of memory cells causes the data, when stored as a word of data, to occupy a register arranged in essentially a diagonal pattern through the array.

Abstract: An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is provided with a semiconductor chip having a memory for storing instruction words, an arithmetic unit, an instruction word decoder for controlling the arithmetic unit in response to instruction commands read out of the instruction word memory and a combined data and flag bit storage system. The combined data and flag bit storage system provides for the storage of flag bits with an associated numeric data word in a single register. Certain of the stages of the register are preferably dedicated for use as flag bit storage and certain other stages of the register are dedicated for use as numeric data storage. The arithmetic unit is preferably operable in a first mode for performing arithmetic operations in binary coded decimal format for the numeric data and in a binary format for the flag bits.

Abstract: An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is provided with a semiconductor chip having an arithmetic unit, a memory register and a dual speed shift register, the dual speed shift register being responsive to control signals generated on the chip for controlling the memory register to selectively read out a first or second number of digits of data stored therein to an input of the arithmetic unit.