Abstract: A user interface allows a user to input handwritten, key-press, and spoken text in a seamless, synchronized manner. A text input panel accepts soft keyboard presses and handwritten words, characters, and gestures. A text recognizer/synchronizer integrates textual input from various sources while recognizing and preserving the order in which a user entered text via the soft keyboard, via handwriting, and/or by speaking. Synchronized text may be displayed in a stage area of the text input panel before being passed to an operating system message router and/or an application program. While in handwriting recognition mode, various permutations and combinations of a word recognition area, a character recognition area, and a keybar/keypad may optionally be displayed.

Abstract: A user interface allows a user to input handwritten, key-press, and spoken text in a seamless, synchronized manner. A text input panel accepts soft keyboard presses and handwritten words, characters, and gestures. A text recognizer/synchronizer integrates textual input from various sources while recognizing and preserving the order in which a user entered text via the soft keyboard, via handwriting, and/or by speaking. Synchronized text may be displayed in a stage area of the text input panel before being passed to an operating system message router and/or an application program. While in handwriting recognition mode, various permutations and combinations of a word recognition area, a character recognition area, and a keybar/keypad may optionally be displayed.

Abstract: A method and apparatus to improve the read/write performance of a hard drive is presented. The hard drive includes solid state, non-volatile (NV) memory as a read/write cache. Data specified by the operating system is stored in the NV memory. The operating system provides a list of data to be put in NV memory. The data includes data to be pinned in NV memory and data that is dynamic. Pinned data persists in NV memory until the operating system commands it to be flushed. Dynamic data can be flushed by the hard drive controller. Data sent by an application for storage is temporary stored in NV memory in data blocks until the operating system commits it to the disk.

Abstract: A pen-based computing system supports organizing, editing, and rendering handwritten digital ink. A given page of text may include several word flows, but the flows may be prevented from overlapping one another, and each word and stroke may be assigned to only one flow on the page. Various functions are available to open up additional space in a flow, to reflow the words in a flow, and to normalize the spacing between words in a flow.

Abstract: In a computer system, a system video adapter and an add-on video adapter generate video signals according to different dimensional characteristics. The dimensional characteristics of the system adapter are calibrated by a calibration unit so that the video signals can simply be merged. The calibration unit comprises a comparator for detecting pixel signals of calibration lines generated by the system adapter at predetermined horizontal and vertical positions of a display device. The comparator, in response to detecting the pixel signals exceeding a predetermined reference signal, cause a latch to store counts of a counter. The counts represent the horizontal and vertical positions of the detected signals. The counts are presented to the add-on video adapter as calibration parameters. The add-on video adapter can use the calibration parameters to generate video signals which can be directly merged with the video signals of the system video adapter.

Abstract: In a computer system, parallel streams of digital data are transmitted from a source to a destination in bursts or packets. At the beginning of each burst all the parallel data signals contain a start bit. Each data signal is received by a deskewing buffer which transmits the data signal through a delay line with multiple taps. At the beginning of each clock cycle the signal value Data(i) at each tap (i) in the delay line is latched. Each resulting latched signal value LData(i) is compared with the latched signal value LData(i+1) for the next tap down the delay line to generate a set of comparison signals C(i). When the start bit of a new burst is received, one of the comparison signals will have a distinct value from all the others, thereby indicating the delay line tap at which the phase of the received data signal is approximately synchronized with the receiver's clock signal.

Abstract: In a data processing system having a plurality of commander nodes and at least one resource node interconnected by a system bus, a bus arbitration technique determines which commander node is to gain control of the system bus to access the resource node. The bus arbitration technique assigns priority levels to all commander nodes, with at least one commander node receiving more than one priority level. Each priority level has an associated signal path. During each arbitration, each contending commander node can activate or assert the signal path associated with its priority level, and the commander node having more than one priority level can assert the signal path associated with any one of its priority levels. All commander nodes monitor all the signal paths to determine the identity of the contending commander node that asserted the signal path associated with the highest priority level among those that were asserted, and, thus, the contending commander node that "won" the arbitration.

Abstract: A computer system includes a plurality of central processing units (CPUs) each of which has a direct napped cache memory. The system also includes a main memory, and one or more display frame buffers. The cache normally operates in a write back mode, whereby updated data is written back to main memory only when a cache block is reallocated to store a new block of data. A tag for each block of data stored in the cache includes a Shared flag which indicates whether the corresponding block of data may be stored in the cache of another CPU. When a block of data stored is modified, it is immediately written to main memory if the tag for that block has an enabled Shared flag. To make the cache operate in a write-through mode for blocks of image data, the system stores an enabled Shared flag in the cache whenever a block of frame buffer data is stored in the cache.

Abstract: The present invention provides a rapid one-to-one match between requesters that must arbitrate for service from one of a number of servers. Each requester presents a set of requests, and the requesters are indifferent to which server is chosen, no priority existing among the requests seen by a particular server. Requests are presented synchronously to all servers to which access is desired. Each server selects precisely one such request, preferably randomly, and asserts a response signal so stating to all requesters. Each requester then selects precisely one incoming grant responses (if any there are), and de-asserts requests to all other servers. This iteration is repeated for a predetermined number of cycles, at which time substantially most of the requested matches will have been made. The iteration algorithm is preferably implemented with choice units, multiplexers, registers and logic units, all of which may be obtained commercially.

Abstract: In a data processing system in which resource units are shared by a plurality of processing units, an arbitration unit is disclosed wherein the priority assigned to each processing unit is dynamically assigned to equalize accessibility to the shared resource. A signal path, associated with each possible level of priority, is coupled to each processor unit. The processor unit applies an activation signal to the signal line associated with the priority of the processing unit when the processing unit has a requirement for the shared resource and an arbitration is being performed to determine access to the resource. During the arbitration procedure, each processing unit requiring access to the shared resource compares the current priority of the associated processing unit to the activation signals on the signal paths to determine when the processing unit can gain access to the shared resource.

Abstract: A packet routing apparatus allows numerous packets to be routed simultaneously through a mesh connected network. The network consists of a number of interconnected switches which are coupled, in turn, to the hosts that are members of the local network. The switches are nonblocking switches that are coupled to each other and to the hosts by a multiplicity of point to point links. Each switch has a routing mechanism for automatically routing received packets toward their specified destinations. For each received packet the router generates a routing mask representing the output links that may be used to route the packet towards its destination. The routing mask includes a broadcast bit. If the broadcast bit is ON, the packet must be simultaneously routed to all of the output links specified by the routing mask. If the broadcast bit is OFF, the packet may be routed on any single one of the links specified by the routing mask.

Abstract: In a multiprocessor computer system, a number of processors are coupled to main memory by a shared memory bus, and one or more of the processors have a two level direct mapped cache memory. When any one processor updates data in a shared portion of the address space, a cache check request signal is transmitted on the shared data bus, which enables all the cache memories to update their contents if necessary. Since both caches are direct mapped, each line of data stored in the first cache is also stored in one of the blocks in the second cache. Each cache has control logic for determining when a specified address location is stored in one of its lines or blocks. To avoid spurious accesses to the first level cache when a cache check is performed, the second cache has a special table which stores a pointer for each line in said first cache array. This pointer denotes the block in the second cache which stores the same data as is stored in the corresponding line of the first cache.

Abstract: A mesh connected local area network provides automatic packet switching and routing between host computers coupled to the network. The network has a multiplicity of cut-through, nonblocking switches, each capable of simultaneously routing a multiplicity of data packets. Low host-to-host latency is achieved through the use of cut-through switches with separate internal buffers for each packet being routed. The switches are interconnected with one another and are coupled to the host computers of the network by point to point full duplex links. While each switch can be coupled to ten or more network members, i.e., switches and hosts, each link is coupled to only two network members and is dedicated to carrying signals therebetween. Whenever a new switch or link is added to the network, and whenever a switch or link fails, the switches in the network automatically reconfigure the network by recomputing the set of legal paths through the network.

Abstract: A system is disclosed for accurately transmitting binary data through a cable. The binary data are encoded into serial pulse signals in which a transition represents a "1" of the binary data and an unchanging voltage level represents a "0" of the binary data. The serial pulse signals may be distorted due to being transmitted over the cable. The received serial pulse signals are time delayed in such a way that there is a crossing point between the received serial pulse signals and the time delayed received serial pulse signals corresponding to each transition of the encoded serial pulse signals. A detector detects the crossing point and recovers the received serial pulse signal shape back to that of the serial pulse signals. An decoding device decodes the recovered serial pulse signals.

Abstract: A circuit and method for the high speed generation and comparison of Hamming codes to enable the correction of an error burst is described. The circuit generates or compares n Hamming codes simultaneously with the data field transmission. Each code word is associated with a data field word comprising every n.sup.th bit. The resultant system corrects error bursts of up to n bits.Additional circuitry is included to enable the correction of error bits in parallel, increasing the system bandwidth.

Abstract: A data processing system includes a disk drive, a disk drive controller, a main memory and a CPU. The main memory has disk command data stored therein in a chain of disk command blocks (DCB's). Each DCB contains a first word pointing to the next DCB in the chain, a second word containing status information and a third word containing command information. A portion of the command word contains a predetermined verification word when the DCB is valid. The CPU includes means for comparing this portion with the predetermined verification word as stored in a constant memory. If the two correspond, the DCB is valid. Each DCB also includes a fourth word pointing to a block of main memory in which header data is stored. Header data defines the address of the recording location of the disk. A fifth word points to a block of main memory in which label data is stored.

Abstract: A data processing apparatus for processing digital data in accordance with a plurality of predetermined tasks of preassigned priority values and identified by a respective plurality of devices connected to the data processing apparatus. Each device is capable of generating the respective task request signal when requiring service by the data processing apparatus.

Abstract: A data processing display system comprises a display device capable of displaying a desired image and including a plurality of points each capable of being selectively illuminated. A main memory storage device is also included in the system and comprises a plurality of addressable storage locations, each location capable of storing a multi-bit display word therein. At least some of the addressable storage locations include in the aggregate a number of bits at least equal to the plurality of points of the display device. A display bit map of the desired image is thus capable of being stored and defined in the at least some addressable storage locations.

Abstract: Apparatus for enabling communications between two or more data processing stations comprising a communication cable arranged in branched segments including taps distributed thereover. Tied to each tap is a transceiver which on the other side connects to an associated interface stage. Each transceiver includes, in addition to the usual transmitter and receiver sections, a gate which compares the data from the interface stage with the data on the cable and indicates whether such are equal. Should such be unequal, an interference between the transceiver and the cable is indicated, disabling the associated transmitter section. Each interface stage tied to such transceiver also includes an input and an output buffer on the other end thereof interfacing with a using device, such input and output buffers storing both the incoming and outgoing data.