Abstract: A portable computer is provided with enhanced power management capabilities. The portable computer includes a power management system which makes a determination as to whether the computer is "user attended" or "user unattended" based upon the position of the display screen in one embodiment. If the display screen is open, then the computer is regarded as being "user attended". In this case, a first timeout delay of I/O inactivity is applied before the computer is permitted to enter a power saving suspend mode. However, if the display screen is closed, then the computer is regarded as being "user unattended". Is this situation, a second timeout delay of I/O inactivity is applied before the computer is allowed to enter the power saving suspend mode. The second timeout delay is generally significantly shorter than the first timeout delay. This technique is found to significantly increase the reliability of I/O activities such as external communications with the computer when the computer is "user unattended".

Abstract: A peripheral bus interface unit is provided that includes a data storage unit for temporarily storing data written from a peripheral unit, and a control unit that executes a write cycle on a system bus to transfer the data into a system memory. The control unit blocks certain communications, such as polling and interrupt communications between a microprocessor and the peripheral device if data temporarily stored within the data storage unit has not yet been transferred to the system memory. In addition, depending upon whether a complete line of data is to be transferred during the write cycle, the control unit either asserts or deasserts a snoop write-back signal. If the snoop write-back signal is asserted, a snoop write-back operation by, for example, a cache controller is allowed. If the snoop write-back signal is deasserted, a snoop write-back operation of the cache controller is suppressed.

Abstract: An interconnection system for electronic devices includes an internal master connecting terminal which is arranged to receive and mate with one of a plurality of available modular interfacing devices. The electronic device includes a system of internally arranged support and housing cavities which are graduated in size to house and support the modular interfacing devices and provide a uniform and contiguous output interface for connection to other electronic and peripheral devices. The modular interfacing devices are designed to accomodate the inclusion of various bus arrangements as well as additional components and circuitry, both active and passive.

Abstract: A cache-based computer system is provided with a snoop control circuit that implements a write-back suppression technique. The snoop control circuit controls the write-back and invalidation of dirty data within a cache memory during a DMA write operation to maintain the integrity of data within the computer system. If an alternate bus master initiates a burst transfer cycle that does not encompass an entire line of valid data, the alternate bus master asserts a snoop write-back signal that causes the snoop control circuit to effectuate the write-back to system memory of a corresponding dirty line in the cache memory. Integrity of the data within the system is thereby maintained. On the other hand, if the alternate bus master initiates a burst transfer cycle that does encompass an entire line of valid data, the altemate bus master deasserts the snoop write-back signal.

Abstract: A system for reducing the amount of power consumed by a battery operated computer device is disclosed. A microcontroller continuously monitors the activity of at least one I/O device and sets an activity state variable (ASV) associated with the I/O device accordingly. Upon each the expiration of a preselected time period, the microcontroller examines the state of the ASV to determine whether the I/O device was active during the expired time period. If so, the I/O device is caused to operate in a full power mode; otherwise, the I/O device is caused to operate in a reduced power consumption mode. In one embodiment, the I/O device is capable of operating in more than one reduced power consumption mode, in which case, responsive to a determination that the I/O device was not active during the expired time period, the I/O device is caused to operate in the next lowest power consumption mode.

Abstract: A digital computer system includes an interface for routing data which permits the transfer of data between mismatched devices. The computer system comprises a processor, memory and an interconnecting data bus, all configured to handle data units of a first data width. Also connected to the data bus is at least one I/O device configured to handle data units of a second data width. By adjusting the width of the data being transferred to match the width of the receiving device or bus, data may be transferred between devices of differing width. To adjust the width, control means are provided which modify the route along which data bytes are transferred based upon the width of the transferring and receiving devices and the direction of transfer are provided.

Abstract: A multi-master digital computer system has a bus, a plurality of master devices connected to the bus, a plurality of slave devices connected to the bus, and a bus controller for arbitrating bus requests by the master devices and for granting the bus to a selected one of the plurality of the master devices. Each master device is capable of originating a bus cycle to transmit data to or receive data from a desired slave device. The bus controller grants the bus to a selected master device which enters an address master state and addresses the desired slave device. The selected master device is transferred to a bus master state where a data transfer to or from the slave device is initiated. The selected master device then transfers to a data master state unless the selected master device wants, and is permitted through an arbiter, to retain control of the bus. The bus controller grants a bus request to a requesting master device through to the arbiter.

Abstract: A computer which carries its BIOS in a Flash EPROM. A UV-EPROM carries a redundant BIOS, which can be overlaid onto the BIOS address space by selection with a physical switch.The BIOS contains a small core software program, at the BIOS entry point, which checks BIOS integrity, and provides for reloading the Flash EPROM's BIOS if needed (from a floppy disk, or by copying the entire contents of the UV-EPROM).