Abstract: In one embodiment, an integrated circuit chip includes a semiconductor substrate, a metal layer formed on the semiconductor substrate, and an unused auxiliary resource that is tied to ground or to a supply voltage such that current does not flow through the resource and power is not dissipated by the resource, wherein the auxiliary resource can be tied into the integrated circuit to modify operation of the chip.

Abstract: A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global transparency timing modeling.