Abstract: A television storage system for editing and special effects equipment in which live video input material is recorded and converted into two parallel streams of real time live video with the input video recorded as compressed segments independently accessible on multiple synchronous disk drives.

Abstract: A reduced viewport feature for a graphics display system allows an operator to observe manipulations on a graphics display of video image planes that are wholly or partially outside a viewing area. A two-dimensional input image plane in the form of a wireframe is transformed to a three-dimensional image plane due to manipulation, such as rotation and/or translation. The resulting three-dimensional image plane is subsequently mapped as a two-dimensional projection onto the graphics display. Transformation matrix coefficients are multiplied by a variable reduction coefficient to cause all points of the image plane to converge toward the center of the graphics display, resulting in the ability to view space which originally was not visible to the operator on an output video monitor.

Abstract: A graphics path display has fixed wireframes representing key positions of an image being manipulated. Inbetween wireframes, dots or dashes are generated according to a defined display rate between sequential key positions. The inbetween wireframes are generated by an algorithm selected by an operator, and are adjusted in realtime as the operator changes variable parameters for the algorithm to present a realtime display of the graphics path defined by the algorithm and parameters.

Abstract: An apparatus for testing circuit board systems utilizing microprocessors which includes means for selectively exercizing each terminal or pin of the board system during each step of the testing protocol. Each step of the protocol can be preselected to operate according to an automatic sequence or according to a preprogrammed manner, or the apparatus may be conditioned to receive a response from the circuit board system at a selected terminal during a selected step of the testing protocol. The testing apparatus further includes an interactive interface to permit the board system under test to control the speed and sequence of the test procedure. The testing apparatus is capable of exercizing the board systems under test in a simulated environment at typically normal operating speeds so that degradation of system performance related to operational speed and other factors found in an operating environment can be analyzed.