Abstract: An intervote modulator (10) includes a majority voting logic unit (12) and an interplex modulator (14). The majority voting logic unit receives plural signal codes (e.g., five codes x1, x2, x3, x4, x5) together with their respective target gains G1, G2, G3, G4, G5 representing the desired transmit power for the individual signal codes. The majority voting logic unit combines three of these five signal codes to form a majority vote composite signal while keeping the other two signal codes uncombined. The majority vote composite signal and the two uncombined signals are then supplied to the interplex modulator as signals s1, s2 and s3. The interplex modulator applies interplex modulation to signals s1, s2 and s3 to form the in-phase and quadrature components of the final composite signal. The majority voting logic unit employs a generalized majority vote involving an interlace of sub-majority votes determined on a chip-by-chip basis.

Abstract: An intervote modulator (10) includes a majority voting logic unit (12) and an interplex modulator (14). The majority voting logic unit receives plural signal codes (e.g., five codes x1, x2, x3, x4, x5) together with their respective target gains G1, G2, G3, G4, G5 representing the desired transmit power for the individual signal codes. The majority voting logic unit combines three of these five signal codes to form a majority vote composite signal while keeping the other two signal codes uncombined. The majority vote composite signal and the two uncombined signals are then supplied to the interplex modulator as signals S1, S2 and S3. The interplex modulator applies interplex modulation to signals S1, S2 and S3 to form the in-phase and quadrature components of the final composite signal. The majority voting logic unit employs a generalized majority vote involving an interlace of sub-majority votes determined on a chip-by-chip basis.