Abstract: A system and method for converting information stored on a magnetic medium to DVD format. A tape transport mechanism may sample information stored on a magnetic medium at a selected rate where the selected rate is correlated to an available buffer size in a data processing system. The rate at which information is sampled may be less than the NTSC standard of 30 frames/second thereby requiring less storage to store the digital video representation. The sampled information may be captured and converted into a digital format. The digitized magnetic waveform may be transferred to the data processing system configured to convert the digitized magnetic signals into digitized television waveforms to recover the analog and video content. The digitized television waveforms may then be converted into a digital video representation. The digitized information may then be temporarily stored in the available buffer prior to being compressed and converted into DVD format.

Abstract: At system power on, a query is sent from a PCI or host-based controller to an attached codec for the vendor specific identification code associated with that codec. The PCI/host controller then sets its PCI vendor and subvendor ID's to match the specific system comprised of the controller and codec devices. That vendor specific identification code is then utilized within the PCI enumeration process to search for the specific modem driver associated with that codec.

Abstract: When a riser card is connected to a computer system motherboard, a storage device on the riser card will contain configuration data permitting the computer system to configure any peripheral device on the riser card. The configuration data will be treated by the BIOS in the computer system as a virtual add-on ROM thereby allowing it to execute and initialize any and all PCI configuration spaces associated with the riser card peripheral devices.

Abstract: A computer system employing a host processor and an emulation coprocessor. The host processor includes hardware configured to execute instructions defined by a host instruction set architecture, while the emulation coprocessor includes hardware configured to execute instructions defined by a different instruction set architecture from the host instruction set architecture (“the foreign instruction set architecture”). The host processor core executes operating system code as well as application programs which are coded in the host instruction set architecture. Upon initiation of a foreign application program, the host processor core communicates with the emulation coprocessor core to cause the emulation coprocessor core to execute the foreign application program. Accordingly, application programs coded according to the foreign instruction set architecture can be executed directly in hardware. The computer system may be characterized as a heterogeneous multiprocessing system.

Abstract: A computer system employing a host processor and an emulation coprocessor. The host processor includes hardware configured to execute instructions defined by a host instruction set architecture, while the emulation coprocessor includes hardware configured to execute instructions defined by a different instruction set architecture from the host instruction set architecture (“the foreign instruction set architecture”). The host processor core executes operating system code as well as application programs which are coded in the host instruction set architecture. Upon initiation of a foreign application program, the host processor core communicates with the emulation coprocessor core to cause the emulation coprocessor core to execute the foreign application program. Accordingly, application programs coded according to the foreign instruction set architecture can be executed directly in hardware. The computer system may be characterized as a heterogeneous multiprocessing system.

Abstract: A computer system includes a host processor and an emulation coprocessor. The host processor includes hardware configured to execute instructions defined by a host instruction set architecture, while the emulation coprocessor includes hardware configured to execute instructions defined by a different instruction set architecture from the host instruction set architecture (“the foreign instruction set architecture”). According to one embodiment, the host processor executes operating system code as well as application programs which are coded in the host instruction set architecture. Upon initiation of a foreign application program, the host processor communicates with the emulation coprocessor to cause the emulation coprocessor to execute the foreign application program. The computer system also includes a bus bridge coupled to the host processor and the emulation coprocessor.

Abstract: A fail-safe device is disclosed for removing power from circuitry to be controlled upon the occurrence of an undesired operating condition. The device includes circuitry for generating a fail-safe signal that is normally within a predetermined frequency range unless there is an undesired operating condition. It also includes power control circuitry for supplying power to the circuitry to be controlled only when the fail-safe signal is within the predetermined frequency range. In a preferred embodiment, the circuitry for generating the fail-safe signal includes a programmable computer which regulates the circuitry to be controlled and which, unless there is an undesired operating condition, such as a failure of the computer, also generates a sequence of bits in which a predetermined pattern occurs at a known frequency. A comparater circuit compares this sequence of bits with the predetermined pattern and generates a variation in the fail-safe signal each time there is a match.