Abstract: A phase-locked loop for PCM transmission systems has a phase comparator (20) which provides continuous regulation of the loop oscillator (30). When a PCM pulse signal is present, the phase comparator selectively compares the PCM and oscillator clock signal and generates an error signal which synchronizes the oscillator to the PCM frequency. During the absence of a PCM pulse, the phase comparator provides a high impedance output and oscillator synchronization is maintained by a loop filter (23). In the disclosed embodiment, the phase comparator is a dual section tristate gate (300).

Abstract: This disclosure relates to a demultiplexer for a pair of digital groups (digroups) which are synchronously multiplexed into a composite signal by bit interleaving the pair. The composite multiplex signal is coupled to each of a pair of gating circuits. A clock recovery circuit recovers the timing of the composite signal and generates therefrom a pair of phase inverted clock signals. These clock signals are respectively coupled to the two gating circuits to alternately enable the same and thereby steer the interleaved digroup bits to separate digroup receive units. A comparison circuit is coupled to each receive unit to compare the relative timing of the bits delivered thereto; this comparison utilizes the fact that multiplexing is done with the bits of one digroup preceding the bits of the other.