Patents by Inventor Charles R. Erickson

Charles R. Erickson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10307244
    Abstract: A polymer coating/ring is employed to aid in the sealing and connection of modular elements used in body flow lumens for the exclusion and bypass of diseased regions of the flow lumen, such as where aneurysm occurs adjacent to branching blood vessels.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: June 4, 2019
    Assignee: Medtronic Vascular, Inc.
    Inventors: Prema Ganesan, Jonathan Morris, David R. Erickson, Matthew Rust, Curtis Hanson, Jack Chu, Charles Thomas
  • Patent number: 7885820
    Abstract: Expert system supported interactive product selection and recommendation. The invention assists an agent to interact with a customer and to provide selection and recommendation of available products and/or services that offer a workable solution for the customer. The invention allows for the use of agents of varying skill levels, including relatively low skill level, without suffering deleterious performance. From certain perspectives, an expert system employed using various aspects of the invention allows the agent to provide real time interaction with a customer and to provide a real time recommended solution to that customer. Many traditional approaches dealing in complex industries require that agent's have a high degree of skill and expertise. The invention allows even a novice agent to service a customer's needs without requiring a high skill level or up-front training that is often at the expense of the provider seeking to market its products and/or services.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: February 8, 2011
    Assignee: Convergys CMG Utah, Inc.
    Inventors: Rod Mancisidor, Charles R. Erickson, Ahmed Gheith, William W. Chan
  • Patent number: 7558773
    Abstract: Expert System supported interactive product selection and recommendation. The invention assists an agent to interact with a customer and to provide selection and recommendation of available products and/or services that offer a workable solution for the customer. The invention allows for the use of agents of varying skill levels, including relatively low skill level, without suffering deleterious performance. From certain perspectives, an expert system employed using various aspects of the invention allows the agent to provide real time interaction with a customer and to provide a real time recommended solution to that customer. Many traditional approaches dealing in complex industries require that agent's have a high degree of skill and expertise. The invention allows even a novice agent to service a customer's needs without requiring a high skill level or up-front training that is often at the expense of the provider seeking to market its products and/or services.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: July 7, 2009
    Assignee: Convergys CMG Utah, Inc.
    Inventors: Rod Mancisidor, Charles R. Erickson, Ahmed Gheith, William W. Chan
  • Patent number: 7031951
    Abstract: An expert system adapted dedicated Internet access guidance engine. The invention allows an agent to interact with a customer and to provide selection and recommendation of data network products and/or services for the customer. The invention allows for the use of agents of varying skill levels, including relatively low skill level, without suffering deleterious performance. The dedicated Internet access guidance engine is operable to perform selection and rating of Internet access products and/or services to provide a solution that meets the needs of a customer. The dedicated Internet access guidance engine is operable to select recommended solutions from among a number of potential solutions that may include compatible solutions. The dedicated Internet access guidance engine is one of the underlying engines within the expert system that allows the agent to provide real time interaction with a customer and to provide a real time recommended solution to that customer.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: April 18, 2006
    Assignee: Convergys Information Management Group, Inc.
    Inventors: Rod Mancisidor, Charles R. Erickson, Gordon Gilpin
  • Patent number: 6745172
    Abstract: An expert system adapted data network guidance engine. The invention allows an agent to interact with a customer and to provide selection and recommendation of data network products and/or services for the customer. The invention allows for the use of agents of varying skill levels, including relatively low skill level, without suffering deleterious performance. The data network guidance engine is operable to perform generation and selection of configurations that are generated using various heuristics. If desired, numerous iterations are performed within each of the heuristic operations. The data network guidance engine is operable to select recommended configurations from among a number of potential options. In addition, compatible configurations may also be identified. The data network guidance engine is one of the underlying engines within the expert system that allows the agent to provide real time interaction with a customer and to provide a real time recommended solution to that customer.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: June 1, 2004
    Assignee: Whisperwire, Inc.
    Inventors: Rod Mancisidor, Rob Norris, Charles R. Erickson, Ahmed Gheith
  • Publication number: 20020116243
    Abstract: An expert system adapted dedicated Internet access guidance engine. The invention allows an agent to interact with a customer and to provide selection and recommendation of data network products and/or services for the customer. The invention allows for the use of agents of varying skill levels, including relatively low skill level, without suffering deleterious performance. The dedicated Internet access guidance engine is operable to perform selection and rating of Internet access products and/or services to provide a solution that meets the needs of a customer. The dedicated Internet access guidance engine is operable to select recommended solutions from among a number of potential solutions that may include compatible solutions. The dedicated Internet access guidance engine is one of the underlying engines within the expert system that allows the agent to provide real time interaction with a customer and to provide a real time recommended solution to that customer.
    Type: Application
    Filed: July 19, 2001
    Publication date: August 22, 2002
    Inventors: Rod Mancisidor, Charles R. Erickson, Gordon Gilpin
  • Patent number: 6212639
    Abstract: A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: April 3, 2001
    Assignee: Xilinx, Inc.
    Inventors: Charles R. Erickson, Danesh Tavana, Victor A. Holen
  • Patent number: 6181158
    Abstract: A structure for providing clearing/programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops. One method for clearing and programming a programmable logic device includes arranging a plurality of memory cells in sets, clearing the sets in a first spatial sequence, and programming the sets in a second spatial sequence. Sets of memory cells could include columns of memory cells, each column having an associated storage element. In this manner, a plurality of columns of memory cells can be cleared or programmed in any predetermined order.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: January 30, 2001
    Assignee: Xilinx, Inc.
    Inventors: Edmond Y. Cheung, Charles R. Erickson
  • Patent number: 6100705
    Abstract: A method and structure for testing static signal levels on an integrated circuit device using an electron beam deflection device. Each static signal is applied to a first terminal of a switch, such as an AND gate, an OR gate, or a pass transistor. An alternating control signal of approximately 1 MHz is transmitted to a second terminal of the switch such that the switch generates an output signal that is either constant (if the static signal is at a first level), or has a frequency equal to that of the alternating control signal (if the static signal is at a second level). The output signal is transmitted to a pad located on an exposed surface of the integrated circuit, where an electron beam deflection device is utilized to determine the static signal level by detecting the presence or absence of an alternating signal. A method for determining the voltage level of a signal includes applying the signal to the gate of a transistor and an alternating control signal to an input terminal.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: August 8, 2000
    Assignee: Xilinx, Inc.
    Inventors: Charles R. Erickson, Brian D. Erickson
  • Patent number: 6057704
    Abstract: A field programmable gate array (FPGA) having an array of configuration memory cells arranged in rows and columns. The configuration memory cells store configuration data values for configuring the FPGA. Each configuration memory cell is coupled to a corresponding row line through a corresponding cell access transistor. A row access circuit is coupled to the row lines. To re-program a first set (but not a second set) of configuration memory cells in a column, the row access circuit initially pre-charges each of the row lines, and then provides configuration data values on a first set (but not a second set) of the row lines. All cell access transistors in the column are coupled to a column select line. To avoid losing data in any memory cell, a relatively low read voltage, followed by a higher write voltage, is applied to the column select line. When the read voltage is applied to the column select line, the associated cell access transistors are weakly turned on.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: May 2, 2000
    Assignee: Xilinx, Inc.
    Inventors: Bernard J. New, Charles R. Erickson
  • Patent number: 5995988
    Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: November 30, 1999
    Assignee: Xilinx, Inc.
    Inventors: Philip M. Freidin, Stephen M. Trimberger, John E. Mahoney, Charles R. Erickson
  • Patent number: 5990704
    Abstract: A multi-state input drive structure is provided to forward externally generated high and low input signals, as well as to receive at least a third, internally generated, comparatively weak signal, preferably an oscillating signal, which triggers a third internally forwarded signal when neither of the high and low input signals is received. The inventive circuit drives three internally forwarded output signals from a single external signal source. Since this circuit may be duplicated for every pin on a device for which two cycle delays do not affect performance, availability of a third input state on N inputs allows 3.sup.N input codes as opposed to 2.sup.N for the conventional "high" and "low" levels normally available.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: November 23, 1999
    Assignee: Xilinx, Inc.
    Inventors: Charles R. Erickson, Brian D. Erickson
  • Patent number: 5970142
    Abstract: A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: October 19, 1999
    Assignee: Xilinx, Inc.
    Inventor: Charles R. Erickson
  • Patent number: 5969543
    Abstract: An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: October 19, 1999
    Assignee: Xilinx, Inc.
    Inventors: Charles R. Erickson, Peter H. Alfke
  • Patent number: 5961576
    Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: October 5, 1999
    Assignee: Xilinx, Inc.
    Inventors: Philip M. Freidin, Stephen M. Trimberger, John E. Mahoney, Charles R. Erickson
  • Patent number: 5923614
    Abstract: A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: July 13, 1999
    Assignee: Xilinx, Inc.
    Inventors: Charles R. Erickson, Robert O. Conn, Lois D. Cartier
  • Patent number: 5920201
    Abstract: In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V.sub.GG level, where V.sub.GG .gtoreq.V.sub.DD +V.sub.TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V.sub.GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: July 6, 1999
    Assignee: Xilinx, Inc.
    Inventors: Alok Mehrotra, Charles R. Erickson
  • Patent number: 5909453
    Abstract: A scan lookahead skip structure that allows a programmable number of test bits, I/O blocks, flip-flops, or columns to be skipped. One embodiment of the structure includes multiplexers to skip the scan paths for several adjacent I/O blocks, flip-flops, or columns, thereby reducing the number of clock cycles and overall delay required to utilize the scan path.
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: June 1, 1999
    Assignee: Xilinx, Inc.
    Inventors: Steven H. Kelem, Charles R. Erickson
  • Patent number: 5844829
    Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.
    Type: Grant
    Filed: December 4, 1997
    Date of Patent: December 1, 1998
    Assignee: Xilinx, Inc
    Inventors: Philip M. Freidin, Stephen M. Trimberger, John E. Mahoney, Charles R. Erickson
  • Patent number: 5838167
    Abstract: An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: November 17, 1998
    Assignee: Xilinx, Inc.
    Inventors: Charles R. Erickson, Lawrence Cy-Wei Hung