Abstract: A system for optimizing RGB digital color images to print a high speed textile conveyed substrate using a series of modular single color specific ink jet print engines. The system mounts a rotary screen upstream and in operable combination with the ink jet print engines consequentially providing a broad array of printing modes and effects. Each print engine extracts print engine specific instructions from a server to provide a sequential cascade of printings to print the desired image. Internetworking extends operable control to remote client and expands RGB image archive to galleries of the World Wide Web. Present commercial rotary screen machines can be retrofitted to utilize the present system.

Abstract: A system and method for optimizing RGB digital color images to print a high speed textile conveyed substrate using a series of modular single color specific ink jet print engines. The system mounts on a rotary screen upstream and in operable combination with the ink jet print engines consequentially providing a broad array of printing modes and effects. Each print engine extracts print engine specific instructions from a server to provide a sequential cascade of printings to print the desired image. Internetworking extends operable control to remote client and expands RGB image archive to galleries of the World Wide Web.

Abstract: The present invention provides a method of printing a digital image on a textile including the steps of selecting 8 to 16 inks to form an ink set, calibrating the ink set to create an ink set profile, using the ink set profile to calculate hue and shade-based look-up tables directly correlating the inks with the color space coordinates of the pixels of the digital image. The present invention also is a system and an apparatus providing a device for performing the calibration of the ink set and direct correlation of the color space coordinates. The printed fabric has a first plurality of dots having 8 to 16 differently colored inks per dot and a second plurality of dots having one color per dot. Significantly, the present invention produces printed textiles having a high detail, deep color, and broad shading, as well as a combination of dyes heretofore considered incompatible.

Abstract: There is provided a method, system, and apparatus of reproducing a digital image on a paper including the steps of the user selecting 8 to 16 inks to form an ink set, calibrating the ink set to create an ink set profile, using the ink set profile to calculate hue-based and/or shade-based look-up tables (LUTs) that directly correlate the inks with the color space coordinates (e.g., RGB values) of the pixels of the digital image. By directly correlating the inks and the color space coordinates using hue and shade, the present method faithfully reproduces the digital image. The method may be practiced using a system and/or apparatus that provides means for performing the calibration of the ink set and direct correlation of the color space coordinates. The printed substrate has a first plurality of dots having 8 to 16 differently colored inks per dot and a second plurality of dots having one color per dot.

Abstract: The present invention provides a method of printing a digital image on a textile including the steps of selecting 8 to 16 inks to form an ink set, calibrating the ink set to create an ink set profile, using the ink set profile to calculate hue and shade-based look-up tables directly correlating the inks with the color space coordinates of the pixels of the digital image. The present invention also is a system and an apparatus providing means for performing the calibration of the ink set and direct correlation of the color space coordinates. The printed fabric has a first plurality of dots having 8 to 16 differently colored inks per dot and a second plurality of dots having one color per dot. Significantly, the present invention produces printed textiles having a high detail, deep color, and broad shading, as well as a combination of dyes heretofore considered incompatible.

Abstract: The present invention provides a method of printing a digital image on a textile including the steps of selecting 8 to 16 inks to form an ink set, calibrating the ink set to create an ink set profile, using the ink set profile to calculate hue and shade-based look-up tables directly correlating the inks with the color space coordinates of the pixels of the digital image. The present invention also is a system and an apparatus providing means for performing the calibration of the ink set and direct correlation of the color space coordinates. The printed fabric has a first plurality of dots having 8 to 16 differently colored inks per dot and a second plurality of dots having one color per dot. Significantly, the present invention produces printed textiles having a high detail, deep color, and broad shading, as well as a combination of dyes heretofore considered incompatible.

Abstract: The present invention provides a method of printing a digital image on a textile including the steps of selecting 8 to 16 inks to form an ink set, calibrating the ink set to create an ink set profile, using the ink set profile to calculate hue and shade-based look-up tables directly correlating the inks with the color space coordinates of the pixels of the digital image. The present invention also is a system and an apparatus providing means for performing the calibration of the ink set and direct correlation of the color space coordinates. The printed fabric has a first plurality of dots having 8 to 16 differently colored inks per dot and a second plurality of dots having one color per dot. Significantly, the present invention produces printed textiles having a high detail, deep color, and broad shading, as well as a combination of dyes heretofore considered incompatible.

Abstract: The present invention provides a method of printing a digital image on a textile including the steps of selecting 8 to 16 inks to form an ink set, calibrating the ink set to create an ink set profile, using the ink set profile to calculate hue and shade-based look-up tables directly correlating the inks with the color space coordinates of the pixels of the digital image. The present invention also is a system and an apparatus performing the calibration of the ink set and direct correlation of the color space coordinates. The printed fabric has a first plurality of dots having 8 to 16 differently colored inks per dot and a second plurality of dots having one color per dot. Significantly, the present invention produces printed textiles having a high detail, deep color, and broad shading, as well as a combination of dyes heretofore considered incompatible.

Abstract: There is provided a method, system, and apparatus of reproducing a digital image on a paper including the steps of the user selecting 8 to 16 inks to form an ink set, calibrating the ink set to create an ink set profile, using the ink set profile to calculate hue-based and/or shade-based look-up tables (LUTs) that directly correlate the inks with the color space coordinates (e.g., RGB values) of the pixels of the digital image. By directly correlating the inks and the color space coordinates using hue and shade, the present method faithfully reproduces the digital image. The method may be practiced using a system and/or apparatus that provides means for performing the calibration of the ink set and direct correlation of the color space coordinates. The printed substrate has a first plurality of dots having 8 to 16 differently colored inks per dot and a second plurality of dots having one color per dot.

Abstract: The present invention provides a method of printing a digital image on a textile including the steps of selecting 8 to 16 inks to form an ink set, calibrating the ink set to create an ink set profile, using the ink set profile to calculate hue and shade-based look-up tables directly correlating the inks with the color space coordinates of the pixels of the digital image. The present invention also is a system and an apparatus providing means for performing the calibration of the ink set and direct correlation of the color space coordinates. The printed fabric has a first plurality of dots having 8 to 16 differently colored inks per dot and a second plurality of dots having one color per dot. Significantly, the present invention produces printed textiles having a high detail, deep color, and broad shading, as well as a combination of dyes heretofore considered incompatible.

Abstract: A process friendly precision voltage generator for use in a digital/analog system or the like, includes a modified phase lock loop (MPLL) and a frequency control system for adjusting the frequency of the MPLL until a desired reference voltage is obtained at an output node of the loop filter. The frequency of the phase lock loop is then locked to the frequency, at which the desired reference voltage has been obtained.

Abstract: A single-port network node transceiver that does not draw any substantial current from the network when it is powered-down, enabling it to meet the ISDN powered-down loading specification when built on a CMOS integrated circuit chip. The pull-up transistors of the transmitter output circuit each have means for shorting the well terminal to source terminal connection when the circuit is operating and opening the connection when the power to the transceiver is shut down. The opening of this connection prevents the well-substrate junction of the pull-up transistors from becoming forward biased and drawing current from the network when the power to the transceiver is off and there is voltage present on the network. The transceiver also includes a plurality of ESD overvoltage protection diodes in series between the power supply rail and each input/output terminal.

Abstract: A phase lock loop circuit (PLL) is manufactured as a part of each very large scale integrated circuit (VLSI) that might need clock pulses. When these VLSI chips are mounted on a printed circuit board (PC), three crystal oscillators are also mounted on the PC in order to provide redundancy. In order to identify crystal oscillators that are less desirable from the standpoint of operation and accuracy, a circuit is mounted on the PC for comparing oscillator frequencies and detecting when lack of frequency agreement is noted. A gating circuit receives the output of the detecting circuit for selecting and passing clock pulses only from a properly functioning crystal oscillator to the rest of the PC. Programmable counters are provided in the PLLs to allow local generation within each VLSI of clock pulses at a frequency that is a ratio of the frequency of the crystal-generated clock pulses that are circulated throughout the PC.

Abstract: The internal electrical noise generated by circuits of a VLSI chip is controlled by separating the logic circuit substrate contacts from the logic circuits ground contacts. A separate return path interconnects each contact to card ground. Further noise reduction is achieved by providing a void region between the noise generating devices and the "quiet" devices. A substrate contact ring is provided in the void region. The substrate contact ring is connected by a separate path to card ground.

Abstract: An adaptive equalization and regeneration system is provided for accurately reconstructing a received data pulse train which has been degraded with respect to amplitude and instantaneous frequency. The system comprises an equalizer which responds to a control signal to provide a variable gain function for the received signal and output an equalized signal, digital phase lock logic for receiving and extracting timing information from the equalized signal, a regenerator for matching the timing information with the equalized signal to reconstruct the received data in its originally transmitted form, and control circuitry for providing the control signal to the equalizer. The control signal adjusts the slope of the equalizer gain function so as to minimize amplitude and instantaneous frequency degradation at the equalizer output. The system includes a mechanism to detect and calculate total signal degradation at the equalizer output.

Abstract: A high current CMOS circuit including a raised cosine signal generator for generating a raised cosine signal waveform and an input circuit arrangement for controlling the raised cosine signal generator is described. The raised cosine signal generator includes an output node to which a controlled chain of CMOS inverters are connected. The input circuit arrangement accepts an input signal, converts it into appropriate signals which drive respective inverters so that simultaneous conduction of inverter pairs is prevented. The off chip driver (OCD) minimizes ground bounce, electrical noise and radiation problems caused by large current transients or spikes (di/dt) that usually accompany such circuits.

Abstract: Described is a circuit arrangement for controlling peak transient current on data buses of VLSI chips. The circuit arrangement includes a phase lock loop (PLL) with a voltage control oscillator (VCO) made up of high speed inverter circuits that generate very short time interval pulses that are used to control the switching sequence of drivers onto the buses. As a result, the transients are distributed over a relatively short time interval and data throughput on the buses is not adversely affected.

Abstract: An improved CMOS signal magnitude detector (SMD) for accurately quantifying the peak-to-peak magnitude of a received signal is disclosed. The SMD includes a precision gain amplifier, positive and negative peak detectors and a switched capacitive amplifier. The recited components are coupled to form a combination circuit arrangement which receives a differential signal and outputs a single ended signal which is compared with a reference signal to provide a control signal when the differential signal is of a sufficient peak to peak voltage magnitude. The control signal may be used to gate the differential signal and generate an output signal representative of received data.

Abstract: A precision gain circuit arrangement for amplifying analog type signals is fabricated on an integrated chip with digital devices in a CMOS process. The circuit arrangement includes a high gain operational amplifier with a series connected pair of FET devices setting a reference voltage (V.sub.ref) at the inverting input of the operational amplifier and a feedback circuit including a parallel connected pair of FET devices and a biasing FET for said pair set the gain of said circuit arrangement.

Abstract: A process insensitive reference voltage generator includes a first and second identical FET devices coupled in a parallel configuration with a first biasing network, of FET devices, interconnecting the substrate terminal of the first FET device to a first node formed between a positive voltage supply and ground potential. The control terminal is connected to a second node whose voltage potential is different from that of the first node. The substrate terminal of the second FET device is connected to the source terminal. The source terminals of both FET devices are connected to the respective input terminals of an operational amplifier whose output is connected to the control terminal of said second FET device.