Abstract: A method of constructing a circuit for communicating electrical signals and assembled at least in part by an automated assembly machine is disclosed. The automated assembly machine is operable to select from a plurality of components. The circuit includes a material having a first and second surface and a length. A strip conductor is positioned along the first surface of the material. A ground structure is disposed along the length of the second surface. Finally, a low impedance device selected from the plurality of components is electrically coupled to the ground structure on opposite sides of the strip conductor, wherein the coupling of the low impedance device to the ground structure forms a circumferential shield around the strip conductor. Various alternative embodiments, as well as fabrication methodology are also disclosed.

Abstract: A circuit for communicating electrical signals and assembled at least in part by an automated assembly machine is disclosed. The automated assembly machine is operable to select from a plurality of components. The circuit includes a material having a first and second surface and a length. A strip conductor is positioned along the first surface of the material. A ground structure is disposed along the length of the second surface. Finally, a low impedance device selected from the plurality of components is electrically coupled to the ground structure on opposite sides of the strip conductor, wherein the coupling of the low impedance device to the ground structure forms a circumferential shield around the strip conductor. Various alternative embodiments, as well as fabrication methodology are also disclosed.

Abstract: When there is a loss of tracking in a signal tracking system, such as a phase-lock loop, some components of the system, such as high gain amplifiers, will tend to have their outputs driven to the rail. When the output of an amplifier used to drive a voltage controlled oscillator in a phase-lock loop is driven to the rail, not only is its gain reduced to a very low value but additionally this rail voltage will interfere with the signal reacquisition process of the system. The present invention detects when system conditions are such that the amplifier could change to a low gain condition, and provides feedback around the high gain amplifier during those conditions to keep its output substantially centered until the system reestablishes a tracking mode.

Abstract: A phase-lock loop system incorporates a normally "transparent" oscillator used in detecting whether or not the system is in a locked condition. It is essential that the oscillator, a portion of which is serially involved in the phase-lock loop, have a long time constant, so as to minimally affect the closed loop's transfer function during phase-locked conditions. It is desirable, however, that when the phase-lock loop loses lock that the time constants of the transparent oscillator change to much smaller values for quick response of the oscillator and operation at a high frequency for detection purposes and quick extinction when phase-lock is acquired. The detection of oscillation of the transparent oscillator initiates the application of a low speed sweep signal being applied to the voltage controlled oscillator portion of the phase-lock loop to reestablish phase-locked conditions and eventually return of the transparent oscillator to its long time constant values.

Abstract: A circuit for generating pseudoerrors when the value of a received digital bit signal enters a pseudoerror region, as may be employed in the control loop of an adaptive system. The circuit includes its own feedback to control the boundaries of the pseudoerror region so that the rate of pseudoerror generation lies within a useful range.

Abstract: An equalizer circuit wherein the equalized signal is at the output of a summing network; one input to the summing network is the signal to be equalized, and the other input is from a feedback network. The output of the summing network serves as an input to a variable gain unclocked decision device which provides a digital input to the feedback network, depending on whether the equalized signal is determined to be a one or a zero. Sucessful equalization is provided, with the unclocked device. Moreover, the variable gain of the decision device permits the equalizer circuit to respond to a control level from an adaptive control network for automatically equalizing individual transmission links.

Abstract: A circuit for adaptively equalizing a digital signal to compensate for distortion introduced by a transmission medium. The circuit includes a first feedback path for modifying the input signal which is to be equalized to an extent controlled by a control input signal. A second feedback path modifies the input signal to an extent which tends to overcompensate the signal for the transmission distortion. Further, means are provided to modify the signal so as to undercompensate it for the transmission distortion. Error detectors detect pseudo bit errors in the overcompensated and the undercompensated signal, and a control input signal is generated for the first feedback path, dependent on the difference between the errors detected in the overcompensated and undercompensated signal.

Abstract: A phase detection function is obtained by performing two series retiming operations on a data input signal in accordance with a local clock and exclusive OR'ing the signals involved in the two retiming operations. The first exclusive OR'ing provides a variable pulse width signal and the second exclusive OR'ing provides a fixed pulse width signal which may be used as a reference. The combination of the two signals can then be used to provide an indication of phase of the clock with respect to the data. By taking the phase detected signal and supplying it in integrated format to a VCO and using the output of the VCO to provide the clock input to the retiming means, a circuit is provided which provides not only data regeneration, but also clock recovery from the data input and assures that the leading edge of the recovered clock is centered between positive going and negative going transitions of the data to be regenerated.

Abstract: A circuit for providing decision feedback equalization uses a variable gain differential amplifier as a level detector and variable gain adjustment to provide nondelayed positive feedback and bit time delayed intersymbol interference compensating feedback to both enhance the amplitude of the present bit and reduce the intersymbol interference of one or more prior bits in a pulse bit stream.

Abstract: The phase of the clock timing pulses are continuously optimized relative to the received signal under the control of pseudo-error detectors.