Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.

Abstract: A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.

Abstract: A method and apparatus for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for the inhibited processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Abstract: A mechanism is provided for enforcing power caps within a power consumption device with multiple power supplies. Utilizing a minimum power error value from a set of error values, the minimum power error value is multiplied by a factor k to translate the minimum power error value to an internal power error value. The internal minimum power error value is multiplied by a number of working power supply units (M) of the power consumption device, resulting in an internal minimum power error value for multiple power supply units. The internal minimum power error value for the multiple power supply units is summed with a present power cap value thereby forming a summed power cap value. Responsive to the summed power cap value being between a power cap maximum and a power cap minimum, the computing load is throttled using the summed power cap value.

Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.

Abstract: A mechanism is provided for power capping power consumption devices with multiple power supplies. A set of power supplies supplying power to a power consumption device having stranded power is determined. A power budget of one or more power supplies in the set of power supplies is adjusted to match a power budget of a power supply in the set of power supplies with a limiting power budget among the power budgets computed for each power supply in the set of power supplies. Responsive to identifying at least one power supply in the one or more other power supplies of one or more different power consumption devices having an initially allocated power budget below their corresponding demand, at least a portion of the stranded power is allocated to the power budget of the at least one power supply.

Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.

Abstract: A mechanism is provided for enforcing power caps within a power consumption device with multiple power supplies. Utilizing a minimum power error value from a set of error values, the minimum power error value is multiplied by a factor k to translate the minimum power error value to an internal power error value. The internal minimum power error value is multiplied by a number of working power supply units (M) of the power consumption device, resulting in an internal minimum power error value for multiple power supply units. The internal minimum power error value for the multiple power supply units is summed with a present power cap value thereby forming a summed power cap value. Responsive to the summed power cap value being between a power cap maximum and a power cap minimum, the computing load is throttled using the summed power cap value.

Abstract: A mechanism is provided for power capping power consumption devices with multiple power supplies. A set of power supplies supplying power to a power consumption device having stranded power is determined. A power budget of one or more power supplies in the set of power supplies is adjusted to match a power budget of a power supply in the set of power supplies with a limiting power budget among the power budgets computed for each power supply in the set of power supplies. Responsive to identifying at least one power supply in the one or more other power supplies of one or more different power consumption devices having an initially allocated power budget below their corresponding demand, at least a portion of the stranded power is allocated to the power budget of the at least one power supply.

Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.

Abstract: A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.

Abstract: A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

Abstract: A method and apparatus for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for the inhibited processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Abstract: A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.

Abstract: A mechanism is provided for throttling power utilized by a set of power consumption devices using priority-aware power capping. Responsive to unassigned power budget remaining in the overall power budget after a minimum power budget value has been assigned to the child device based on an associated priority of the child device, an additional power budget value equal to a remaining priority-based exposed power demand value of the child device is assigned to the child device in response to the remaining unassigned power budget being greater than or equal to the remaining priority-based demanded power value thereby forming a total power budget for the child device. Responsive to design limitations of power distribution equipment in the data processing system or contractual limits of the data processing system being reached, a throttling is implemented by each child device based on the total power budget assigned to the child device.

Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.

Abstract: A remote debugging technique provides anonymity of program variables and selective debugging capability by providing a registration facility by which program variables are registered locally with a debugging module. An external program then communicates with the debugging modules and observes and/or modifies the program variables by specifying either an index or a variable name. The need to publish symbols is thereby averted and only the variables that a developer is interested in observing need be registered.