Abstract: Methods for removing an oxide film from a silicon-on-insulator structure are disclosed. The oxide may be stripped from a SOI structure before deposition of an epitaxial silicon thickening layer. The oxide film may be removed by dispensing an etching solution toward a center region of the SOI structure and dispensing an etching solution to an edge region of the structure.

Abstract: Methods for removing an oxide film from a silicon-on-insulator structure are disclosed. The oxide may be stripped from a SOI structure before deposition of an epitaxial silicon thickening layer. The oxide film may be removed by dispensing an etching solution toward a center region of the SOI structure and dispensing an etching solution to an edge region of the structure.

Abstract: Methods for removing an oxide film from a silicon-on-insulator structure are disclosed. The oxide may be stripped from a SOI structure before deposition of an epitaxial silicon thickening layer. The oxide film may be removed by dispensing an etching solution toward a center region of the SOI structure and dispensing an etching solution to an edge region of the structure.

Abstract: Methods for removing an oxide film from a silicon-on-insulator structure are disclosed. The oxide may be stripped from a SOI structure before deposition of an epitaxial silicon thickening layer. The oxide film may be removed by dispensing an etching solution toward a center region of the SOI structure and dispensing an etching solution to an edge region of the structure.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Abstract: Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the ion-implanted donor wafer to cause a portion of the ions to out-diffuse prior to wafer bonding. The donor structure may be bonded to a handle structure and cleaved without re-implanting ions into the donor structure.

Abstract: Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the ion-implanted donor wafer to cause a portion of the ions to out-diffuse prior to wafer bonding. The donor structure may be bonded to a handle structure and cleaved without re-implanting ions into the donor structure.

Abstract: A low pressure in situ wafer cleaning process and apparatus are disclosed wherein a low pressure external combustion reactor 2 in combination with a low pressure furnace 14 produces a stream of a combustion product through the combustion of a halogenated hydrocarbon and oxygen. The combustion product is contacted with semiconductor wafers in the low pressure furnace to remove Group I and II metals. After a sufficient time has passed for cleaning, the combustion reactor and furnace are purged with an inert gas to remove the combustion product. In a preferred embodiment, the halogenated hydrocarbon is trans-1,2-dichloroethylene and the combustion product is vaporous hydrochloric acid.

Abstract: A reactor for depositing an epitaxial layer on a semiconductor wafer contained within the reactor during a chemical vapor deposition process. The reactor comprises a reaction chamber sized and shaped for receiving a semiconductor wafer and an inlet passage in communication with the reaction chamber for delivering reactant gas to the reaction chamber. In addition the reactor includes a susceptor positioned in the reaction chamber for supporting the semiconductor wafer during the chemical vapor deposition process. Further, the reactor comprises an injector including a metering plate generally blocking reactant gas flow through the inlet passage. The plate has a slot extending through the plate totally within a periphery of the plate. The slot is sized for selectively restricting reactant gas flow past the plate thereby to meter reactant gas delivery to the chamber.