Abstract: An operating mechanism for laterally moving a slide-out section relative to a vehicle between a retracted position and an extended position includes a rack and pinion assembly mounted to a frame. The pinion preferably has a non-round hole through which a non-round drive shaft is received in driving engagement. The pinion is received in a channel with sides of the channel adjacent to the sides of the pinion. The pinion floats axially on the drive shaft and the sides of the channel maintain the axial position of the pinion on the drive shaft. The shape of the drive shaft and the hole in the pinion is preferably square.

Abstract: The instruction pipeline of a processor, which includes execution circuitry and instruction sequencing logic, receives a stream of instructions including a pipeline interlocking test instruction. The processor includes pipeline control logic that, responsive to receipt of the test instruction, interlocks the instruction pipeline as specified in the test instruction to prevent advancement of at least one first instruction in the instruction pipeline while permitting advancement of at least one second instruction in the instruction pipeline until occurrence of a release condition also specified by the test instruction. In response to the release condition, the pipeline control logic releases the interlock to enable advancement of said at least one instruction in the instruction pipeline.

Abstract: The instruction pipeline of a processor, which includes execution circuitry and instruction sequencing logic, receives a stream of instructions including a pipeline interlocking test instruction. The processor includes pipeline control logic that, responsive to receipt of the test instruction, interlocks the instruction pipeline as specified in the test instruction to prevent advancement of at least one first instruction in the instruction pipeline while permitting advancement of at least one second instruction in the instruction pipeline until occurrence of a release condition also specified by the test instruction. In response to the release condition, the pipeline control logic releases the interlock to enable advancement of said at least one instruction in the instruction pipeline.

Abstract: A method and system are provided for transferring information between multiple buses. Information is transferred through a first bus between multiple first bus devices. Information is transferred through a second bus between multiple second bus devices. Information is transferred through logic between the first and second buses. Using the logic, an action of a first bus device is enabled in response to a condition in which a second bus device waits for the action while the first bus device waits for a separate action on the second bus.

Abstract: A method and system in a data processing system for transferring data from a first device to a second device within the data processing system. The data processing system includes a data bus, an address bus, a first address space associated with a memory and a second address space associated with an input/output device. Initially, a transfer signal is transmitted in the data processing system. The transfer signal identifies the transfer as a transfer concerning an address in the second address space associated with the input/output device. A first address package is then transmitted to the second device from the first device on the address bus. The first address package includes a transfer identifier, a first identifier associated with the first device and a second identifier associated with the second device. A second address package, comprising a byte count and an address, are transmitted to the second device from the first device on the address bus.

Abstract: A method and system for distributed instruction address translation in a multiscalar data processing system having multiple processor units for executing multiple tasks, instructions and data stored within memory at real addresses therein and a fetcher unit for fetching and dispatching instructions to the processor units. A memory management unit (MMU) is established which includes a translation buffer and translation algorithms for implementing page table and address block type translations of every effective address within the data processing system into real addresses within memory. A translation array, which includes a small number of translation objects for translating effective addresses into real addresses, is then established within the fetcher unit. The translation objects are periodically and selectively varied, utilizing the translation capability of the memory management unit (MMU), in response to a failure to translate an effective address into a real address within the fetcher unit.

Abstract: Translation lookaside buffers (TLB) are often utilized in the data processing system to efficiently translate an effective or virtual address to a real address within system memory. In systems which include multiple processors which may all access system memory, each processor may include a translation lookaside buffer (TLB) for translating effective addresses to real addresses and coherency between all translation lookaside buffers (TLB) must therefore be maintained. The method and system disclosed herein may be utilized to broadcast a unique bus structure in response to an execution of a translation lookaside buffer invalidate (TLBI) instruction by any processor within a multiprocessor system. The bus structure is accepted by other processors along the bus only in response to an absence of a pending translation lookaside buffer invalidate (TLBI) instruction within each processor.

Abstract: A data processing system including a circuit for storing a sequence of instructions, a circuit for determining if the instruction sequence includes a branch instruction, a circuit for storing a sequence of branch target instructions in response to the determination of the existence of a branch instruction in the stored sequence of instructions, a circuit for dispatching instructions in sequence after the branch instruction to a processor to be executed on condition that a branch is to be taken before a determination of whether said branch will be taken and simultaneously for determining if the branch is to be taken, any circuit for directing the processor to execute the instructions in sequence after the branch if the branch is not taken, or, if the branch is to be taken, for dispatching the branch target instruction sequence to the processor for execution.

Abstract: A buffer for storing data words consisting of several storage locations together with circuitry providing a first indicator that designates the next storage location to be stored into, a second indicator designating the next storage location to be retrieved from, and circuitry that provides the number of locations available for storage and the number of locations available for retrieval. Furthermore, the buffer includes the capability to store and retrieve several data words simultaneously.

Abstract: A portable electric lamp generally designed to connect to the electrical supply system in an automobile. The portable electric lamp as a base and a pair of feet pivotally secured to the base at spaced locations thereon and about parallel axes. A U-shaped bracket having a pair of upstanding and parallel legs and a bight portion is pivotally secured to the base for movement about a first pivot axis. A lamp holding casing is received between the upstanding legs of the bracket and is pivotally connected to each of the legs of the bracket to support the lamp holding casing for moving about a second pivot axis perpendicular to the first pivot axis. The lamp holding casing includes structure for releasably holding at least one lamp or sealed beam bulb therein. An electrical cord having an electrical probe thereon is provided for connecting the lamp to a source of electrical energy.

Abstract: This invention relates to a communication system wherein a plurality of stations can communicate with each other, without going through a central switchboard; and more particularly to such a communication system that is as private as possible -- the commmunication system having, in addition, the capability of conference calls and a command-override.

Abstract: A voltage regulator apparatus for controlling a voltage at the output side of a line in accordance with variations of the voltage at the input side of the line. The voltage regulator includes a transformer having a primary winding and a secondary winding, the secondary winding being inserted in the line. Control circuitry is provided for controlling the switching of the primary winding to the input side of the line, which control circuitry includes a series connected saturable inductor having a predefined saturation level and a rectifier connected to the input side of the line. Sensing circuitry is provided which is responsive to a predefined voltage at the output of the rectifier occurring when the inductor is in the saturated condition, the sensing circuitry being nonresponsive to the voltage at the output terminal of the rectifier when the inductor is in an unsaturated state.

Abstract: A ramp current method of sensitivity testing allows a dynamic record to be btained of the current, voltage, and energy, as well as resistance and instantaneous power necessary to fire electroexplosive devices. This method is most valuable in that useful information is gained from each firing and thus only minimum sampling is utilized. The ramp method also allows a defective item to be detected rather than recorded as a less sensitive device and therefore as an erroneous data point, contributing to more accurate firing data.