Abstract: An ESD protection circuit allows a certain level of ESD current to flow through a protected circuit, and actuates a bypass path for greater ESD current levels when the sensed current reaches a threshold level. For a protected circuit having a pair of differential input terminals and a reference voltage terminal, the bypass path is provided between an input terminal which receives an ESD and the reference voltage terminal when the reference voltage is fixed, and between the two input terminals when the reference voltage is floating. The bypass circuit is preferably implemented with a pair of bipolar transistors of a first conductivity that are actuated by an ESD current flow through the protected circuit, and a pair of bipolar transistors of opposite conductivity that are actuated by current flows through the first conductivity transistors.

Abstract: A circuit arrangement for synchronizing source data from a source system with a clock and/or clocks from a sink system. The circuit arrangement includes a source counter, a buffer, a sink counter and a controller. The source data is placed in consecutive buffer positions under the control of the source counter. The sink counter is made to "follow" the source counter and identifies the location in the buffer whereat output data is to be extracted. The controller monitors the counters and generates control signals representative of the state of the buffer.