Abstract: Data is transferred from a host system to a subsystem connected to the host by a system bus in an efficient manner using one or more virtual first in first out (FIFO) registers in host memory and a corresponding set of virtual FIFOs located in the subsystem memory. A transmission controller controls the transfer of data from the host FIFOs to the subsystem FIFOs while the subsystem processor reads and processes data from the subsystem FIFO. By accumulating data in the host FIFOs before transfer to the subsystem, overhead associated with starting and stopping data transfers over the system bus is substantially reduced.

Abstract: A graphics adapter having a processor for processing pixel data is provided. The processor transfers the processed data to the graphics memory in sets of slices of pixel data where each transfer provides several slices, each slice being from a unique pixel. In an alternative embodiment, the storage of the processed data is accomplished within a plurality of memory banks, each of the memory banks being used to store slices of consecutive pixels. The invention further provides for concurrently displaying images having different color depths. This is achieved by a method of organizing data of different pixel depths such that they can be interpreted correctly. Furthermore, the invention provides for double buffering the processed data to get a smooth transition from one image to another.