Abstract: A first plurality of D-type flip flops are connected in cascade to store successively a plurality of different adjacent CVSD bits of a first of two CVSD bit streams. A second plurality of D-type flip flops store successively a plurality of different adjacent CVSD bits of a second of two CVSD bit streams. Each of the plurality of bits of the two bit streams are capable of having a plurality of different CVSD bit combinations. Logic circuitry is coupled to the first and second plurality of D-type flip flops to simultaneously assign a different slope number to each of the plurality of different combinations of the two CVSD bit streams and to add the slope numbers of the two CVSD bit streams to provide a sum CVSD bit stream at the output of the adder.